# =======================================================================================
#
#      Filename:  perfmon_nvidiagrace_events.txt
#
#      Description:  Event list for Nvidia Grace CPU
#
#      Version:   5.4.1
#      Released:  09.12.2024
#
#      Author:   Thomas Gruber (tr), thomas.roehl@googlemail.com
#      Project:  likwid
#
#      Copyright (C) 2024 RRZE, University Erlangen-Nuremberg
#
#      This program is free software: you can redistribute it and/or modify it under
#      the terms of the GNU General Public License as published by the Free Software
#      Foundation, either version 3 of the License, or (at your option) any later
#      version.
#
#      This program is distributed in the hope that it will be useful, but WITHOUT ANY
#      WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
#      PARTICULAR PURPOSE.  See the GNU General Public License for more details.
#
#      You should have received a copy of the GNU General Public License along with
#      this program.  If not, see <http://www.gnu.org/licenses/>.
#
# =======================================================================================

EVENT_SW_INCR 0x00 PMC
UMASK_SW_INCR 0x00

EVENT_L1I_CACHE_REFILL 0x01 PMC
UMASK_L1I_CACHE_REFILL 0x00

EVENT_L1I_TLB_REFILL 0x02 PMC
UMASK_L1I_TLB_REFILL 0x00

EVENT_L1D_CACHE_REFILL 0x03 PMC
UMASK_L1D_CACHE_REFILL 0x00

EVENT_L1D_CACHE 0x04 PMC
UMASK_L1D_CACHE 0x00

EVENT_L1D_TLB_REFILL 0x05 PMC
UMASK_L1D_TLB_REFILL 0x00

EVENT_INST_RETIRED 0x08 PMC
UMASK_INST_RETIRED 0x00

EVENT_EXC_TAKEN 0x09 PMC
UMASK_EXC_TAKEN 0x00

EVENT_EXC_RETURN 0x0A PMC
UMASK_EXC_RETURN 0x00

EVENT_CID_WRITE_RETIRED 0x0B PMC
UMASK_CID_WRITE_RETIRED 0x00

EVENT_BR_MIS_PRED 0x10 PMC
UMASK_BR_MIS_PRED 0x00

EVENT_CPU_CYCLES 0x11 PMC
UMASK_CPU_CYCLES 0x00

EVENT_BR_PRED 0x12 PMC
UMASK_BR_PRED 0x00

EVENT_MEM_ACCESS 0x13 PMC
UMASK_MEM_ACCESS 0x00

EVENT_L1I_CACHE 0x14 PMC
UMASK_L1I_CACHE 0x00

EVENT_L1D_CACHE_WB 0x15 PMC
UMASK_L1D_CACHE_WB 0x00

EVENT_L2D_CACHE 0x16 PMC
UMASK_L2D_CACHE 0x00

EVENT_L2D_CACHE_REFILL 0x17 PMC
UMASK_L2D_CACHE_REFILL 0x00

EVENT_L2D_CACHE_WB 0x18 PMC
UMASK_L2D_CACHE_WB 0x00

EVENT_BUS_ACCESS 0x19 PMC
UMASK_BUS_ACCESS 0x00

EVENT_MEMORY_ERROR 0x1A PMC
UMASK_MEMORY_ERROR 0x00

EVENT_INST_SPEC  0x1B PMC
UMASK_INST_SPEC  0x00

EVENT_TTBR_WRITE_RETIRED  0x1C  PMC
UMASK_TTBR_WRITE_RETIRED  0x00

EVENT_BUS_CYCLES    0x1D  PMC
UMASK_BUS_CYCLES    0x00

EVENT_COUNTER_OVERFLOW         0x1E PMC
UMASK_COUNTER_OVERFLOW         0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_ALLOCATE 0x20 PMC
UMASK_L2D_CACHE_ALLOCATE 0x00

EVENT_CACHE_ALLOCATE 0x20 PMC
UMASK_CACHE_ALLOCATE 0x00

EVENT_BR_RETIRED 0x21 PMC
UMASK_BR_RETIRED 0x00

EVENT_BR_MIS_PRED_RETIRED 0x22 PMC
UMASK_BR_MIS_PRED_RETIRED 0x00

EVENT_STALL_FRONTEND 0x23 PMC
UMASK_STALL_FRONTEND 0x00

EVENT_STALL_BACKEND 0x24 PMC
UMASK_STALL_BACKEND 0x00

EVENT_L1D_TLB 0x25 PMC
UMASK_L1D_TLB 0x00

EVENT_L1I_TLB 0x26 PMC
UMASK_L1I_TLB 0x00

EVENT_L3D_CACHE_ALLOCATE 0x29 PMC
UMASK_L3D_CACHE_ALLOCATE 0x00

EVENT_L3D_CACHE_REFILL 0x2A PMC
UMASK_L3D_CACHE_REFILL 0x00

EVENT_L3D_CACHE 0x2B PMC
UMASK_L3D_CACHE 0x00

EVENT_L2D_TLB_REFILL 0x2D PMC
UMASK_L2D_TLB_REFILL 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_TLB 0x2F PMC
UMASK_L2D_TLB 0x00

EVENT_L2TLB_REQ 0x2F PMC
UMASK_L2TLB_REQ 0x00

EVENT_REMOTE_ACCESS 0x31 PMC
UMASK_REMOTE_ACCESS 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_DTLB_WALK 0x34 PMC
UMASK_DTLB_WALK 0x00

EVENT_DTLB_WLK 0x34 PMC
UMASK_DTLB_WLK 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_ITLB_WALK 0x35 PMC
UMASK_ITLB_WALK 0x00

EVENT_ITLB_WLK 0x35 PMC
UMASK_ITLB_WLK 0x00

EVENT_LL_CACHE_RD 0x36 PMC
UMASK_LL_CACHE_RD 0x00

EVENT_LL_CACHE_MISS_RD 0x37 PMC
UMASK_LL_CACHE_MISS_RD 0x00

EVENT_L1D_CACHE_LMISS_RD 0x39 PMC
UMASK_L1D_CACHE_LMISS_RD 0x00

EVENT_OP_RETIRED 0x3A PMC
UMASK_OP_RETIRED 0x00

EVENT_OP_SPEC   0x3B PMC
UMASK_OP_SPEC   0x00

EVENT_STALL     0x3C PMC
UMASK_STALL     0x00

EVENT_STALL_SLOT_BACKEND    0x3D PMC
UMASK_STALL_SLOT_BACKEND    0x00

EVENT_STALL_SLOT_FRONTEND   0x3E PMC
UMASK_STALL_SLOT_FRONTEND   0x00

EVENT_STALL_SLOT            0x3F PMC
UMASK_STALL_SLOT            0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L1D_CACHE_LD  0x40 PMC
UMASK_L1D_CACHE_LD  0x00

EVENT_L1D_CACHE_RD  0x40 PMC
UMASK_L1D_CACHE_RD  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L1D_CACHE_ST  0x41 PMC
UMASK_L1D_CACHE_ST  0x00

EVENT_L1D_CACHE_WR  0x41 PMC
UMASK_L1D_CACHE_WR  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L1D_CACHE_REFILL_LD  0x42 PMC
UMASK_L1D_CACHE_REFILL_LD  0x00

EVENT_L1D_CACHE_REFILL_RD  0x42 PMC
UMASK_L1D_CACHE_REFILL_RD  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L1D_CACHE_REFILL_ST  0x43 PMC
UMASK_L1D_CACHE_REFILL_ST  0x00

EVENT_L1D_CACHE_REFILL_WR  0x43 PMC
UMASK_L1D_CACHE_REFILL_WR  0x00

EVENT_L1D_CACHE_REFILL_INNER 0x44 PMC
UMASK_L1D_CACHE_REFILL_INNER 0x00

EVENT_L1D_CACHE_REFILL_OUTER 0x45 PMC
UMASK_L1D_CACHE_REFILL_OUTER 0x00

EVENT_L1D_CACHE_WB_VICTIM  0x46 PMC
UMASK_L1D_CACHE_WB_VICTIM  0x00

EVENT_L1D_CACHE_WB_CLEAN  0x47 PMC
UMASK_L1D_CACHE_WB_CLEAN  0x00

EVENT_L1D_CACHE_INVAL  0x48 PMC
UMASK_L1D_CACHE_INVAL  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L1D_TLB_REFILL_LD  0x4C PMC
UMASK_L1D_TLB_REFILL_LD  0x00

EVENT_L1D_TLB_REFILL_RD  0x4C PMC
UMASK_L1D_TLB_REFILL_RD  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L1D_TLB_REFILL_ST  0x4D PMC
UMASK_L1D_TLB_REFILL_ST  0x00

EVENT_L1D_TLB_REFILL_WR  0x4D PMC
UMASK_L1D_TLB_REFILL_WR  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L1D_TLB_LD 0x4E PMC
UMASK_L1D_TLB_LD 0x00

EVENT_L1D_TLB_RD 0x4E PMC
UMASK_L1D_TLB_RD 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L1D_TLB_ST 0x4F PMC
UMASK_L1D_TLB_ST 0x00

EVENT_L1D_TLB_WR 0x4F PMC
UMASK_L1D_TLB_WR 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_LD  0x50 PMC
UMASK_L2D_CACHE_LD  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_RD  0x50 PMC
UMASK_L2D_CACHE_RD  0x00

EVENT_CACHE_ACCESS_RD  0x50 PMC
UMASK_CACHE_ACCESS_RD  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_ST  0x51 PMC
UMASK_L2D_CACHE_ST  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_WR  0x51 PMC
UMASK_L2D_CACHE_WR  0x00

EVENT_CACHE_ACCESS_WR  0x51 PMC
UMASK_CACHE_ACCESS_WR  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_REFILL_LD  0x52 PMC
UMASK_L2D_CACHE_REFILL_LD  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_REFILL_RD  0x52 PMC
UMASK_L2D_CACHE_REFILL_RD  0x00

EVENT_CACHE_RD_REFILL  0x52 PMC
UMASK_CACHE_RD_REFILL  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_REFILL_ST  0x53 PMC
UMASK_L2D_CACHE_REFILL_ST  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_REFILL_WR  0x53 PMC
UMASK_L2D_CACHE_REFILL_WR  0x00

EVENT_CACHE_WR_REFILL  0x53 PMC
UMASK_CACHE_WR_REFILL  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_WB_VICTIM  0x56 PMC
UMASK_L2D_CACHE_WB_VICTIM  0x00

EVENT_CACHE_WRITEBACK_VICTIM  0x56 PMC
UMASK_CACHE_WRITEBACK_VICTIM  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_WB_CLEAN  0x57 PMC
UMASK_L2D_CACHE_WB_CLEAN  0x00

EVENT_CACHE_WRITEBACK_CLEAN_COH  0x57 PMC
UMASK_CACHE_WRITEBACK_CLEAN_COH  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_INVAL  0x58 PMC
UMASK_L2D_CACHE_INVAL  0x00

EVENT_L2CACHE_INV  0x58 PMC
UMASK_L2CACHE_INV  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_TLB_REFILL_LD 0x5C PMC
UMASK_L2D_TLB_REFILL_LD 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_TLB_REFILL_RD 0x5C PMC
UMASK_L2D_TLB_REFILL_RD 0x00

EVENT_L2TLB_RD_REFILL 0x5C PMC
UMASK_L2TLB_RD_REFILL 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_TLB_REFILL_ST 0x5D PMC
UMASK_L2D_TLB_REFILL_ST 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_TLB_REFILL_WR 0x5D PMC
UMASK_L2D_TLB_REFILL_WR 0x00

EVENT_L2TLB_WR_REFILL 0x5D PMC
UMASK_L2TLB_WR_REFILL 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_TLB_LD 0x5E PMC
UMASK_L2D_TLB_LD 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_TLB_RD 0x5E PMC
UMASK_L2D_TLB_RD 0x00

EVENT_L2TLB_RD_REQ 0x5E PMC
UMASK_L2TLB_RD_REQ 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_TLB_ST 0x5F PMC
UMASK_L2D_TLB_ST 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_TLB_WR 0x5F PMC
UMASK_L2D_TLB_WR 0x00

EVENT_L2TLB_WR_REQ 0x5F PMC
UMASK_L2TLB_WR_REQ 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_BUS_ACCESS_LD  0x60 PMC
UMASK_BUS_ACCESS_LD  0x00

EVENT_BUS_ACCESS_RD  0x60 PMC
UMASK_BUS_ACCESS_RD  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_BUS_ACCESS_ST  0x61 PMC
UMASK_BUS_ACCESS_ST  0x00

EVENT_BUS_ACCESS_WR  0x61 PMC
UMASK_BUS_ACCESS_WR  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_MEM_ACCESS_LD  0x66 PMC
UMASK_MEM_ACCESS_LD  0x00

EVENT_MEM_ACCESS_RD  0x66 PMC
UMASK_MEM_ACCESS_RD  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_MEM_ACCESS_ST  0x67 PMC
UMASK_MEM_ACCESS_ST  0x00

EVENT_MEM_ACCESS_WR  0x67 PMC
UMASK_MEM_ACCESS_WR  0x00

EVENT_UNALIGNED_LD_SPEC  0x68 PMC
UMASK_UNALIGNED_LD_SPEC  0x00

EVENT_UNALIGNED_ST_SPEC  0x69 PMC
UMASK_UNALIGNED_ST_SPEC  0x00

EVENT_UNALIGNED_LDST_SPEC  0x6A PMC
UMASK_UNALIGNED_LDST_SPEC  0x00

EVENT_LDREX_SPEC  0x6C PMC
UMASK_LDREX_SPEC  0x00

EVENT_STREX_PASS_SPEC  0x6D PMC
UMASK_STREX_PASS_SPEC  0x00

EVENT_STREX_FAIL_SPEC  0x6E PMC
UMASK_STREX_FAIL_SPEC  0x00

EVENT_STREX_SPEC 0x6F PMC
UMASK_STREX_SPEC 0x00

EVENT_LD_SPEC  0x70 PMC
UMASK_LD_SPEC  0x00

EVENT_ST_SPEC  0x71 PMC
UMASK_ST_SPEC  0x00

EVENT_DP_SPEC  0x73 PMC
UMASK_DP_SPEC  0x00

EVENT_ASE_SPEC  0x74 PMC
UMASK_ASE_SPEC  0x00

EVENT_VFP_SPEC  0x75 PMC
UMASK_VFP_SPEC  0x00

EVENT_PC_WRITE_SPEC  0x76 PMC
UMASK_PC_WRITE_SPEC  0x00

EVENT_CRYPTO_SPEC  0x77 PMC
UMASK_CRYPTO_SPEC  0x00

EVENT_BR_IMMED_SPEC  0x78 PMC
UMASK_BR_IMMED_SPEC  0x00

EVENT_BR_RETURN_SPEC  0x79 PMC
UMASK_BR_RETURN_SPEC  0x00

EVENT_BR_INDIRECT_SPEC  0x7A PMC
UMASK_BR_INDIRECT_SPEC  0x00

EVENT_ISB_SPEC  0x7C PMC
UMASK_ISB_SPEC  0x00

EVENT_DSB_SPEC  0x7D PMC
UMASK_DSB_SPEC  0x00

EVENT_DMB_SPEC  0x7E PMC
UMASK_DMB_SPEC  0x00

EVENT_EXC_UNDEF  0x81 PMC
UMASK_EXC_UNDEF  0x00

EVENT_EXC_SVC  0x82 PMC
UMASK_EXC_SVC  0x00

EVENT_EXC_PABORT  0x83 PMC
UMASK_EXC_PABORT  0x00

EVENT_EXC_DABORT  0x84 PMC
UMASK_EXC_DABORT  0x00

EVENT_EXC_IRQ  0x86 PMC
UMASK_EXC_IRQ  0x00

EVENT_EXC_FIQ  0x87 PMC
UMASK_EXC_FIQ  0x00

EVENT_EXC_SMC  0x88 PMC
UMASK_EXC_SMC  0x00

EVENT_EXC_HVC  0x8A PMC
UMASK_EXC_HVC  0x00

EVENT_EXC_TRAP_PABORT  0x8B PMC
UMASK_EXC_TRAP_PABORT  0x00

EVENT_EXC_TRAP_DABORT  0x8C PMC
UMASK_EXC_TRAP_DABORT  0x00

EVENT_EXC_TRAP_OTHER  0x8D PMC
UMASK_EXC_TRAP_OTHER  0x00

EVENT_EXC_TRAP_IRQ  0x8E PMC
UMASK_EXC_TRAP_IRQ  0x00

EVENT_EXC_TRAP_FIQ  0x8F PMC
UMASK_EXC_TRAP_FIQ  0x00

EVENT_RC_LD_SPEC  0x90 PMC
UMASK_RC_LD_SPEC  0x00

EVENT_RC_ST_SPEC  0x91 PMC
UMASK_RC_ST_SPEC  0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L3_CACHE_LD 0xA0 PMC
UMASK_L3_CACHE_LD 0x00

EVENT_L3_CACHE_RD 0xA0 PMC
UMASK_L3_CACHE_RD 0x00

EVENT_CNT_CYCLES  0x4004 PMC
UMASK_CNT_CYCLES

EVENT_STALL_BACKEND_MEM 0x4005 PMC
UMASK_STALL_BACKEND_MEM 0x00

EVENT_L1I_CACHE_LMISS   0x4006 PMC
UMASK_L1I_CACHE_LMISS   0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L2D_CACHE_LMISS_LD    0x4009 PMC
UMASK_L2D_CACHE_LMISS_LD    0x00

EVENT_L2D_CACHE_LMISS_RD    0x4009 PMC
UMASK_L2D_CACHE_LMISS_RD    0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_L3D_CACHE_LMISS_LD    0x400B PMC
UMASK_L3D_CACHE_LMISS_LD    0x00

EVENT_L3D_CACHE_LMISS_RD    0x400B PMC
UMASK_L3D_CACHE_LMISS_RD    0x00

EVENT_TRB_WRAP              0x400C PMC
UMASK_TRB_WRAP              0x00

EVENT_TRCEXTOUT0            0x4010 PMC
UMASK_TRCEXTOUT0            0x00

EVENT_TRCEXTOUT1            0x4011 PMC
UMASK_TRCEXTOUT1            0x00

EVENT_TRCEXTOUT2            0x4012 PMC
UMASK_TRCEXTOUT2            0x00

EVENT_TRCEXTOUT3            0x4013 PMC
UMASK_TRCEXTOUT3            0x00

EVENT_CTI_TRIGOUT4          0x4018 PMC
UMASK_CTI_TRIGOUT4          0x00

EVENT_CTI_TRIGOUT5          0x4019 PMC
UMASK_CTI_TRIGOUT5          0x00

EVENT_CTI_TRIGOUT6          0x401A PMC
UMASK_CTI_TRIGOUT6          0x00

EVENT_CTI_TRIGOUT7          0x401B PMC
UMASK_CTI_TRIGOUT7          0x00

EVENT_LDST_ALIGN_LAT        0x4020 PMC
UMASK_LDST_ALIGN_LAT        0x00

EVENT_LD_ALIGN_LAT          0x4021 PMC
UMASK_LD_ALIGN_LAT          0x00

EVENT_ST_ALIGN_LAT          0x4022 PMC
UMASK_ST_ALIGN_LAT          0x00

EVENT_MEM_ACCESS_CHECKED    0x4024 PMC
UMASK_MEM_ACCESS_CHECKED    0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_MEM_ACCESS_LD_CHECKED 0x4025 PMC
UMASK_MEM_ACCESS_LD_CHECKED 0x00

EVENT_MEM_ACCESS_RD_CHECKED 0x4025 PMC
UMASK_MEM_ACCESS_RD_CHECKED 0x00

# Added by Thomas Gruber to fit previous architectures
EVENT_MEM_ACCESS_ST_CHECKED 0x4026 PMC
UMASK_MEM_ACCESS_ST_CHECKED 0x00

EVENT_MEM_ACCESS_WR_CHECKED 0x4026 PMC
UMASK_MEM_ACCESS_WR_CHECKED 0x00

EVENT_ASE_INST_SPEC         0x8005 PMC
UMASK_ASE_INST_SPEC         0x00

EVENT_SVE_INST_SPEC         0x8006 PMC
UMASK_SVE_INST_SPEC         0x00

EVENT_FP_HP_SPEC            0x8014 PMC
UMASK_FP_HP_SPEC            0x00

EVENT_FP_SP_SPEC            0x8018 PMC
UMASK_FP_SP_SPEC            0x00

EVENT_FP_DP_SPEC            0x801C PMC
UMASK_FP_DP_SPEC            0x00

EVENT_SVE_PRED_SPEC         0x8074 PMC
UMASK_SVE_PRED_SPEC         0x00

EVENT_SVE_PRED_EMPTY_SPEC   0x8075 PMC
UMASK_SVE_PRED_EMPTY_SPEC   0x00

EVENT_SVE_PRED_FULL_SPEC    0x8076 PMC
UMASK_SVE_PRED_FULL_SPEC    0x00

EVENT_SVE_PRED_PARTIAL_SPEC 0x8077 PMC
UMASK_SVE_PRED_PARTIAL_SPEC 0x00

EVENT_SVE_PRED_NOT_FULL_SPEC    0x8079 PMC
UMASK_SVE_PRED_NOT_FULL_SPEC    0x00

EVENT_SVE_LDFF_SPEC         0x80BC PMC
UMASK_SVE_LDFF_SPEC         0x00

EVENT_SVE_LDFF_FAULT_SPEC   0x80BD PMC
UMASK_SVE_LDFF_FAULT_SPEC   0x00

EVENT_FP_SCALE_OPS_SPEC     0x80C0 PMC
UMASK_FP_SCALE_OPS_SPEC     0x00

EVENT_FP_FIXED_OPS_SPEC     0x80C1 PMC
UMASK_FP_FIXED_OPS_SPEC     0x00

EVENT_ASE_SVE_INT8_SPEC     0x80E3 PMC
UMASK_ASE_SVE_INT8_SPEC     0x00

EVENT_ASE_SVE_INT16_SPEC    0x80E7 PMC
UMASK_ASE_SVE_INT16_SPEC    0x00

EVENT_ASE_SVE_INT32_SPEC    0x80EB PMC
UMASK_ASE_SVE_INT32_SPEC    0x00

EVENT_ASE_SVE_INT64_SPEC    0x80EF PMC
UMASK_ASE_SVE_INT64_SPEC    0x00


######### SCF events #####################

EVENT_BUS_CYCLES            0x1D SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_BUS_CYCLES            0x00

EVENT_CYCLES                0x100000000 SCFFIX
UMASK_CYCLES                0x00

EVENT_CMEM_DL_ACCESS 0x1A9 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_DL_ACCESS 0x00

EVENT_CMEM_DL_OUTSTANDING 0x1AA SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_DL_OUTSTANDING 0x00

EVENT_CMEM_DL_RSP 0x1A8 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_DL_RSP 0x00

EVENT_CMEM_EV_ACCESS 0x1AF SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_EV_ACCESS 0x00

EVENT_CMEM_EV_OUTSTANDING 0x1B0 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_EV_OUTSTANDING 0x00

EVENT_CMEM_EV_RSP 0x1AE SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_EV_RSP 0x00

EVENT_CMEM_RD_ACCESS 0x1A6 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_RD_ACCESS 0x00

EVENT_CMEM_RD_DATA 0x1A5 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_RD_DATA 0x00

EVENT_CMEM_RD_OUTSTANDING 0x1A7 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_RD_OUTSTANDING 0x00

EVENT_CMEM_WB_ACCESS 0x1AC SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_WB_ACCESS 0x00

EVENT_CMEM_WB_DATA 0x1AB SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_WB_DATA 0x00

EVENT_CMEM_WB_OUTSTANDING 0x1AD SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_WB_OUTSTANDING 0x00

EVENT_CMEM_WR_ACCESS 0x1CA SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_WR_ACCESS 0x00

EVENT_CMEM_WR_DATA 0x1B1 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_WR_DATA 0x00

EVENT_CMEM_WR_OUTSTANDING 0x1B2 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_WR_OUTSTANDING 0x00

EVENT_CMEM_WR_TOTAL_BYTES 0x1DB SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_CMEM_WR_TOTAL_BYTES 0x00

EVENT_GMEM_DL_ACCESS 0x171 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_DL_ACCESS 0x00

EVENT_GMEM_DL_OUTSTANDING 0x172 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_DL_OUTSTANDING 0x00

EVENT_GMEM_DL_RSP 0x170 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_DL_RSP 0x00

EVENT_GMEM_EV_ACCESS 0x177 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_EV_ACCESS 0x00

EVENT_GMEM_EV_OUTSTANDING 0x178 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_EV_OUTSTANDING 0x00

EVENT_GMEM_EV_RSP 0x176 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_EV_RSP 0x00

EVENT_GMEM_RD_ACCESS 0x16e SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_RD_ACCESS 0x00

EVENT_GMEM_RD_DATA 0x16d SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_RD_DATA 0x00

EVENT_GMEM_RD_OUTSTANDING 0x16f SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_RD_OUTSTANDING 0x00

EVENT_GMEM_WB_ACCESS 0x174 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_WB_ACCESS 0x00

EVENT_GMEM_WB_DATA 0x173 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_WB_DATA 0x00

EVENT_GMEM_WB_OUTSTANDING 0x175 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_WB_OUTSTANDING 0x00

EVENT_GMEM_WR_ACCESS 0x17b SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_WR_ACCESS 0x00

EVENT_GMEM_WR_DATA 0x179 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_WR_DATA 0x00

EVENT_GMEM_WR_OUTSTANDING 0x17a SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_WR_OUTSTANDING 0x00

EVENT_GMEM_WR_TOTAL_BYTES 0x1a0 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_GMEM_WR_TOTAL_BYTES 0x00

EVENT_OCU_0_CMEM_RD_ACCESS 0x1b7 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_CMEM_RD_ACCESS 0x00

EVENT_OCU_0_CMEM_RD_DATA 0x1b3 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_CMEM_RD_DATA 0x00

EVENT_OCU_0_CMEM_RD_OUTSTANDING 0x1bf SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_CMEM_RD_OUTSTANDING 0x00

EVENT_OCU_0_CMEM_WB_ACCESS 0x1bb SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_CMEM_WB_ACCESS 0x00

EVENT_OCU_0_CMEM_WB_DATA 0x1cf SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_CMEM_WB_DATA 0x00

EVENT_OCU_0_CMEM_WB_OUTSTANDING 0x1d7 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_CMEM_WB_OUTSTANDING 0x00

EVENT_OCU_0_CMEM_WR_ACCESS 0x1cb SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_CMEM_WR_ACCESS 0x00

EVENT_OCU_0_CMEM_WR_DATA 0x1d3 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_CMEM_WR_DATA 0x00

EVENT_OCU_0_CMEM_WR_OUTSTANDING 0x1c3 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_CMEM_WR_OUTSTANDING 0x00

EVENT_OCU_0_GMEM_RD_ACCESS 0x149 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_GMEM_RD_ACCESS 0x00

EVENT_OCU_0_GMEM_RD_DATA 0x145 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_GMEM_RD_DATA 0x00

EVENT_OCU_0_GMEM_RD_OUTSTANDING 0x151 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_GMEM_RD_OUTSTANDING 0x00

EVENT_OCU_0_GMEM_WB_ACCESS 0x14d SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_GMEM_WB_ACCESS 0x00

EVENT_OCU_0_GMEM_WB_DATA 0x184 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_GMEM_WB_DATA 0x00

EVENT_OCU_0_GMEM_WB_OUTSTANDING 0x18c SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_GMEM_WB_OUTSTANDING 0x00

EVENT_OCU_0_GMEM_WR_ACCESS 0x188 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_GMEM_WR_ACCESS 0x00

EVENT_OCU_0_GMEM_WR_DATA 0x180 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_GMEM_WR_DATA 0x00

EVENT_OCU_0_GMEM_WR_OUTSTANDING 0x155 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_GMEM_WR_OUTSTANDING 0x00

EVENT_OCU_0_REM_RD_ACCESS 0x15d SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_REM_RD_ACCESS 0x00

EVENT_OCU_0_REM_RD_DATA 0x159 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_REM_RD_DATA 0x00

EVENT_OCU_0_REM_RD_OUTSTANDING 0x165 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_REM_RD_OUTSTANDING 0x00

EVENT_OCU_0_REM_WB_ACCESS 0x161 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_REM_WB_ACCESS 0x00

EVENT_OCU_0_REM_WB_DATA 0x194 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_REM_WB_DATA 0x00

EVENT_OCU_0_REM_WB_OUTSTANDING 0x19c SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_REM_WB_OUTSTANDING 0x00

EVENT_OCU_0_REM_WR_ACCESS 0x198 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_REM_WR_ACCESS 0x00

EVENT_OCU_0_REM_WR_DATA 0x190 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_REM_WR_DATA 0x00

EVENT_OCU_0_REM_WR_OUTSTANDING 0x169 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_0_REM_WR_OUTSTANDING 0x00

EVENT_OCU_1_CMEM_RD_ACCESS 0x1b8 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_CMEM_RD_ACCESS 0x00

EVENT_OCU_1_CMEM_RD_DATA 0x1b4 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_CMEM_RD_DATA 0x00

EVENT_OCU_1_CMEM_RD_OUTSTANDING 0x1c0 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_CMEM_RD_OUTSTANDING 0x00

EVENT_OCU_1_CMEM_WB_ACCESS 0x1bc SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_CMEM_WB_ACCESS 0x00

EVENT_OCU_1_CMEM_WB_DATA 0x1d0 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_CMEM_WB_DATA 0x00

EVENT_OCU_1_CMEM_WB_OUTSTANDING 0x1d8 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_CMEM_WB_OUTSTANDING 0x00

EVENT_OCU_1_CMEM_WR_ACCESS 0x1cc SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_CMEM_WR_ACCESS 0x00

EVENT_OCU_1_CMEM_WR_DATA 0x1d4 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_CMEM_WR_DATA 0x00

EVENT_OCU_1_CMEM_WR_OUTSTANDING 0x1c4 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_CMEM_WR_OUTSTANDING 0x00

EVENT_OCU_1_GMEM_RD_ACCESS 0x14a SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_GMEM_RD_ACCESS 0x00

EVENT_OCU_1_GMEM_RD_DATA 0x146 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_GMEM_RD_DATA 0x00

EVENT_OCU_1_GMEM_RD_OUTSTANDING 0x152 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_GMEM_RD_OUTSTANDING 0x00

EVENT_OCU_1_GMEM_WB_ACCESS 0x14e SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_GMEM_WB_ACCESS 0x00

EVENT_OCU_1_GMEM_WB_DATA 0x185 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_GMEM_WB_DATA 0x00

EVENT_OCU_1_GMEM_WB_OUTSTANDING 0x18d SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_GMEM_WB_OUTSTANDING 0x00

EVENT_OCU_1_GMEM_WR_ACCESS 0x189 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_GMEM_WR_ACCESS 0x00

EVENT_OCU_1_GMEM_WR_DATA 0x181 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_GMEM_WR_DATA 0x00

EVENT_OCU_1_GMEM_WR_OUTSTANDING 0x156 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_GMEM_WR_OUTSTANDING 0x00

EVENT_OCU_1_REM_RD_ACCESS 0x15e SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_REM_RD_ACCESS 0x00

EVENT_OCU_1_REM_RD_DATA 0x15a SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_REM_RD_DATA 0x00

EVENT_OCU_1_REM_RD_OUTSTANDING 0x166 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_REM_RD_OUTSTANDING 0x00

EVENT_OCU_1_REM_WB_ACCESS 0x162 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_REM_WB_ACCESS 0x00

EVENT_OCU_1_REM_WB_DATA 0x195 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_REM_WB_DATA 0x00

EVENT_OCU_1_REM_WB_OUTSTANDING 0x19d SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_REM_WB_OUTSTANDING 0x00

EVENT_OCU_1_REM_WR_ACCESS 0x199 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_REM_WR_ACCESS 0x00

EVENT_OCU_1_REM_WR_DATA 0x191 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_REM_WR_DATA 0x00

EVENT_OCU_1_REM_WR_OUTSTANDING 0x16a SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_1_REM_WR_OUTSTANDING 0x00

EVENT_OCU_2_CMEM_RD_ACCESS 0x1b9 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_CMEM_RD_ACCESS 0x00

EVENT_OCU_2_CMEM_RD_DATA 0x1b5 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_CMEM_RD_DATA 0x00

EVENT_OCU_2_CMEM_RD_OUTSTANDING 0x1c1 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_CMEM_RD_OUTSTANDING 0x00

EVENT_OCU_2_CMEM_WB_ACCESS 0x1bd SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_CMEM_WB_ACCESS 0x00

EVENT_OCU_2_CMEM_WB_DATA 0x1d1 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_CMEM_WB_DATA 0x00

EVENT_OCU_2_CMEM_WB_OUTSTANDING 0x1d9 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_CMEM_WB_OUTSTANDING 0x00

EVENT_OCU_2_CMEM_WR_ACCESS 0x1cd SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_CMEM_WR_ACCESS 0x00

EVENT_OCU_2_CMEM_WR_DATA 0x1d5 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_CMEM_WR_DATA 0x00

EVENT_OCU_2_CMEM_WR_OUTSTANDING 0x1c5 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_CMEM_WR_OUTSTANDING 0x00

EVENT_OCU_2_GMEM_RD_ACCESS 0x14b SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_GMEM_RD_ACCESS 0x00

EVENT_OCU_2_GMEM_RD_DATA 0x147 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_GMEM_RD_DATA 0x00

EVENT_OCU_2_GMEM_RD_OUTSTANDING 0x153 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_GMEM_RD_OUTSTANDING 0x00

EVENT_OCU_2_GMEM_WB_ACCESS 0x14f SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_GMEM_WB_ACCESS 0x00

EVENT_OCU_2_GMEM_WB_DATA 0x186 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_GMEM_WB_DATA 0x00

EVENT_OCU_2_GMEM_WB_OUTSTANDING 0x18e SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_GMEM_WB_OUTSTANDING 0x00

EVENT_OCU_2_GMEM_WR_ACCESS 0x18a SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_GMEM_WR_ACCESS 0x00

EVENT_OCU_2_GMEM_WR_DATA 0x182 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_GMEM_WR_DATA 0x00

EVENT_OCU_2_GMEM_WR_OUTSTANDING 0x157 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_GMEM_WR_OUTSTANDING 0x00

EVENT_OCU_2_REM_RD_ACCESS 0x15f SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_REM_RD_ACCESS 0x00

EVENT_OCU_2_REM_RD_DATA 0x15b SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_REM_RD_DATA 0x00

EVENT_OCU_2_REM_RD_OUTSTANDING 0x167 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_REM_RD_OUTSTANDING 0x00

EVENT_OCU_2_REM_WB_ACCESS 0x163 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_REM_WB_ACCESS 0x00

EVENT_OCU_2_REM_WB_DATA 0x196 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_REM_WB_DATA 0x00

EVENT_OCU_2_REM_WB_OUTSTANDING 0x19e SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_REM_WB_OUTSTANDING 0x00

EVENT_OCU_2_REM_WR_ACCESS 0x19a SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_REM_WR_ACCESS 0x00

EVENT_OCU_2_REM_WR_DATA 0x192 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_REM_WR_DATA 0x00

EVENT_OCU_2_REM_WR_OUTSTANDING 0x16b SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_2_REM_WR_OUTSTANDING 0x00

EVENT_OCU_3_CMEM_RD_ACCESS 0x1ba SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_CMEM_RD_ACCESS 0x00

EVENT_OCU_3_CMEM_RD_DATA 0x1b6 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_CMEM_RD_DATA 0x00

EVENT_OCU_3_CMEM_RD_OUTSTANDING 0x1c2 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_CMEM_RD_OUTSTANDING 0x00

EVENT_OCU_3_CMEM_WB_ACCESS 0x1be SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_CMEM_WB_ACCESS 0x00

EVENT_OCU_3_CMEM_WB_DATA 0x1d2 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_CMEM_WB_DATA 0x00

EVENT_OCU_3_CMEM_WB_OUTSTANDING 0x1da SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_CMEM_WB_OUTSTANDING 0x00

EVENT_OCU_3_CMEM_WR_ACCESS 0x1ce SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_CMEM_WR_ACCESS 0x00

EVENT_OCU_3_CMEM_WR_DATA 0x1d6 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_CMEM_WR_DATA 0x00

EVENT_OCU_3_CMEM_WR_OUTSTANDING 0x1c6 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_CMEM_WR_OUTSTANDING 0x00

EVENT_OCU_3_GMEM_RD_ACCESS 0x14c SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_GMEM_RD_ACCESS 0x00

EVENT_OCU_3_GMEM_RD_DATA 0x148 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_GMEM_RD_DATA 0x00

EVENT_OCU_3_GMEM_RD_OUTSTANDING 0x154 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_GMEM_RD_OUTSTANDING 0x00

EVENT_OCU_3_GMEM_WB_ACCESS 0x150 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_GMEM_WB_ACCESS 0x00

EVENT_OCU_3_GMEM_WB_DATA 0x187 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_GMEM_WB_DATA 0x00

EVENT_OCU_3_GMEM_WB_OUTSTANDING 0x18f SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_GMEM_WB_OUTSTANDING 0x00

EVENT_OCU_3_GMEM_WR_ACCESS 0x18b SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_GMEM_WR_ACCESS 0x00

EVENT_OCU_3_GMEM_WR_DATA 0x183 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_GMEM_WR_DATA 0x00

EVENT_OCU_3_GMEM_WR_OUTSTANDING 0x158 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_GMEM_WR_OUTSTANDING 0x00

EVENT_OCU_3_REM_RD_ACCESS 0x160 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_REM_RD_ACCESS 0x00

EVENT_OCU_3_REM_RD_DATA 0x15c SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_REM_RD_DATA 0x00

EVENT_OCU_3_REM_RD_OUTSTANDING 0x168 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_REM_RD_OUTSTANDING 0x00

EVENT_OCU_3_REM_WB_ACCESS 0x164 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_REM_WB_ACCESS 0x00

EVENT_OCU_3_REM_WB_DATA 0x197 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_REM_WB_DATA 0x00

EVENT_OCU_3_REM_WB_OUTSTANDING 0x19f SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_REM_WB_OUTSTANDING 0x00

EVENT_OCU_3_REM_WR_ACCESS 0x19b SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_REM_WR_ACCESS 0x00

EVENT_OCU_3_REM_WR_DATA 0x193 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_REM_WR_DATA 0x00

EVENT_OCU_3_REM_WR_OUTSTANDING 0x16c SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_3_REM_WR_OUTSTANDING 0x00

EVENT_OCU_PRB_ACCESS 0x1c7 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_PRB_ACCESS 0x00

EVENT_OCU_PRB_DATA 0x1c8 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_PRB_DATA 0x00

EVENT_OCU_PRB_OUTSTANDING 0x1c9 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_OCU_PRB_OUTSTANDING 0x00

EVENT_REMOTE_SOCKET_RD_ACCESS 0x1a4 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_REMOTE_SOCKET_RD_ACCESS 0x00

EVENT_REMOTE_SOCKET_RD_DATA 0x1a2 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_REMOTE_SOCKET_RD_DATA 0x00

EVENT_REMOTE_SOCKET_RD_OUTSTANDING 0x1a3 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_REMOTE_SOCKET_RD_OUTSTANDING 0x00

EVENT_REMOTE_SOCKET_WR_TOTAL_BYTES 0x1a1 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_REMOTE_SOCKET_WR_TOTAL_BYTES 0x00

EVENT_SCF_CACHE 0xf2 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SCF_CACHE 0x00

EVENT_SCF_CACHE_ALLOCATE 0xf0 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SCF_CACHE_ALLOCATE 0x00

EVENT_SCF_CACHE_REFILL 0xf1 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SCF_CACHE_REFILL 0x00

EVENT_SCF_CACHE_WB 0xf3 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SCF_CACHE_WB 0x00

EVENT_SOCKET_0_DL_ACCESS 0x131 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_DL_ACCESS 0x00

EVENT_SOCKET_0_DL_OUTSTANDING 0x119 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_DL_OUTSTANDING 0x00

EVENT_SOCKET_0_DL_RSP 0x105 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_DL_RSP 0x00

EVENT_SOCKET_0_EV_ACCESS 0x13d SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_EV_ACCESS 0x00

EVENT_SOCKET_0_EV_OUTSTANDING 0x125 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_EV_OUTSTANDING 0x00

EVENT_SOCKET_0_EV_RSP 0x10d SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_EV_RSP 0x00

EVENT_SOCKET_0_PRB_ACCESS 0x141 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_PRB_ACCESS 0x00

EVENT_SOCKET_0_PRB_DATA 0x111 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_PRB_DATA 0x00

EVENT_SOCKET_0_PRB_OUTSTANDING 0x129 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_PRB_OUTSTANDING 0x00

EVENT_SOCKET_0_RD_ACCESS 0x12d SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_RD_ACCESS 0x00

EVENT_SOCKET_0_RD_DATA 0x101 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_RD_DATA 0x00

EVENT_SOCKET_0_RD_OUTSTANDING 0x115 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_RD_OUTSTANDING 0x00

EVENT_SOCKET_0_WB_ACCESS 0x135 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_WB_ACCESS 0x00

EVENT_SOCKET_0_WB_DATA 0x109 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_WB_DATA 0x00

EVENT_SOCKET_0_WB_OUTSTANDING 0x11d SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_WB_OUTSTANDING 0x00

EVENT_SOCKET_0_WR_ACCESS 0x139 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_WR_ACCESS 0x00

EVENT_SOCKET_0_WR_DATA 0x17c SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_WR_DATA 0x00

EVENT_SOCKET_0_WR_OUTSTANDING 0x121 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_0_WR_OUTSTANDING 0x00

EVENT_SOCKET_1_DL_ACCESS 0x132 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_DL_ACCESS 0x00

EVENT_SOCKET_1_DL_OUTSTANDING 0x11a SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_DL_OUTSTANDING 0x00

EVENT_SOCKET_1_DL_RSP 0x106 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_DL_RSP 0x00

EVENT_SOCKET_1_EV_ACCESS 0x13e SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_EV_ACCESS 0x00

EVENT_SOCKET_1_EV_OUTSTANDING 0x126 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_EV_OUTSTANDING 0x00

EVENT_SOCKET_1_EV_RSP 0x10e SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_EV_RSP 0x00

EVENT_SOCKET_1_PRB_ACCESS 0x142 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_PRB_ACCESS 0x00

EVENT_SOCKET_1_PRB_DATA 0x112 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_PRB_DATA 0x00

EVENT_SOCKET_1_PRB_OUTSTANDING 0x12a SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_PRB_OUTSTANDING 0x00

EVENT_SOCKET_1_RD_ACCESS 0x12e SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_RD_ACCESS 0x00

EVENT_SOCKET_1_RD_DATA 0x102 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_RD_DATA 0x00

EVENT_SOCKET_1_RD_OUTSTANDING 0x116 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_RD_OUTSTANDING 0x00

EVENT_SOCKET_1_WB_ACCESS 0x136 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_WB_ACCESS 0x00

EVENT_SOCKET_1_WB_DATA 0x10a SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_WB_DATA 0x00

EVENT_SOCKET_1_WB_OUTSTANDING 0x11e SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_WB_OUTSTANDING 0x00

EVENT_SOCKET_1_WR_ACCESS 0x13a SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_WR_ACCESS 0x00

EVENT_SOCKET_1_WR_DATA 0x17d SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_WR_DATA 0x00

EVENT_SOCKET_1_WR_OUTSTANDING 0x122 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_1_WR_OUTSTANDING 0x00

EVENT_SOCKET_2_DL_ACCESS 0x133 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_DL_ACCESS 0x00

EVENT_SOCKET_2_DL_OUTSTANDING 0x11b SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_DL_OUTSTANDING 0x00

EVENT_SOCKET_2_DL_RSP 0x107 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_DL_RSP 0x00

EVENT_SOCKET_2_EV_ACCESS 0x13f SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_EV_ACCESS 0x00

EVENT_SOCKET_2_EV_OUTSTANDING 0x127 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_EV_OUTSTANDING 0x00

EVENT_SOCKET_2_EV_RSP 0x10f SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_EV_RSP 0x00

EVENT_SOCKET_2_PRB_ACCESS 0x143 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_PRB_ACCESS 0x00

EVENT_SOCKET_2_PRB_DATA 0x113 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_PRB_DATA 0x00

EVENT_SOCKET_2_PRB_OUTSTANDING 0x12b SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_PRB_OUTSTANDING 0x00

EVENT_SOCKET_2_RD_ACCESS 0x12f SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_RD_ACCESS 0x00

EVENT_SOCKET_2_RD_DATA 0x103 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_RD_DATA 0x00

EVENT_SOCKET_2_RD_OUTSTANDING 0x117 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_RD_OUTSTANDING 0x00

EVENT_SOCKET_2_WB_ACCESS 0x137 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_WB_ACCESS 0x00

EVENT_SOCKET_2_WB_DATA 0x10b SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_WB_DATA 0x00

EVENT_SOCKET_2_WB_OUTSTANDING 0x11f SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_WB_OUTSTANDING 0x00

EVENT_SOCKET_2_WR_ACCESS 0x13b SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_WR_ACCESS 0x00

EVENT_SOCKET_2_WR_DATA 0x17e SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_WR_DATA 0x00

EVENT_SOCKET_2_WR_OUTSTANDING 0x123 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_2_WR_OUTSTANDING 0x00

EVENT_SOCKET_3_DL_ACCESS 0x134 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_DL_ACCESS 0x00

EVENT_SOCKET_3_DL_OUTSTANDING 0x11c SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_DL_OUTSTANDING 0x00

EVENT_SOCKET_3_DL_RSP 0x108 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_DL_RSP 0x00

EVENT_SOCKET_3_EV_ACCESS 0x140 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_EV_ACCESS 0x00

EVENT_SOCKET_3_EV_OUTSTANDING 0x128 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_EV_OUTSTANDING 0x00

EVENT_SOCKET_3_EV_RSP 0x110 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_EV_RSP 0x00

EVENT_SOCKET_3_PRB_ACCESS 0x144 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_PRB_ACCESS 0x00

EVENT_SOCKET_3_PRB_DATA 0x114 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_PRB_DATA 0x00

EVENT_SOCKET_3_PRB_OUTSTANDING 0x12c SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_PRB_OUTSTANDING 0x00

EVENT_SOCKET_3_RD_ACCESS 0x130 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_RD_ACCESS 0x00

EVENT_SOCKET_3_RD_DATA 0x104 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_RD_DATA 0x00

EVENT_SOCKET_3_RD_OUTSTANDING 0x118 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_RD_OUTSTANDING 0x00

EVENT_SOCKET_3_WB_ACCESS 0x138 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_WB_ACCESS 0x00

EVENT_SOCKET_3_WB_DATA 0x10c SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_WB_DATA 0x00

EVENT_SOCKET_3_WB_OUTSTANDING 0x120 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_WB_OUTSTANDING 0x00

EVENT_SOCKET_3_WR_ACCESS 0x13c SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_WR_ACCESS 0x00

EVENT_SOCKET_3_WR_DATA 0x17f SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_WR_DATA 0x00

EVENT_SOCKET_3_WR_OUTSTANDING 0x124 SCF0|SCF1|SCF2|SCF3|SCF4|SCF5
UMASK_SOCKET_3_WR_OUTSTANDING 0x00


############## (C)NvLink events ################

EVENT_CYCLES 0x100000000 CNVFIX|NV0FIX|NV1FIX|PCIEFIX
UMASK_CYCLES 0x00

EVENT_RD_BYTES_LOC 0x00 CNV|NV0C|NV1C|PCIE
UMASK_RD_BYTES_LOC 0x00

EVENT_RD_BYTES_REM 0x01 CNV|NV0C|NV1C|PCIE
UMASK_RD_BYTES_REM 0x00

EVENT_RD_CUM_OUTS_LOC 0x0C CNV|NV0C|NV1C|PCIE
UMASK_RD_CUM_OUTS_LOC 0x00

EVENT_RD_CUM_OUTS_REM 0x0D CNV|NV0C|NV1C|PCIE
UMASK_RD_CUM_OUTS_REM 0x00

EVENT_RD_REQ_LOC 0x06 CNV|NV0C|NV1C|PCIE
UMASK_RD_REQ_LOC 0x00

EVENT_RD_REQ_REM 0x07 CNV|NV0C|NV1C|PCIE
UMASK_RD_REQ_REM 0x00

EVENT_TOTAL_BYTES_LOC 0x04 CNV|NV0C|NV1C|PCIE
UMASK_TOTAL_BYTES_LOC 0x00

EVENT_TOTAL_BYTES_REM 0x05 CNV|NV0C|NV1C|PCIE
UMASK_TOTAL_BYTES_REM 0x00

EVENT_TOTAL_REQ_LOC 0x0A CNV|NV0C|NV1C|PCIE
UMASK_TOTAL_REQ_LOC 0x00

EVENT_TOTAL_REQ_REM 0x0B CNV|NV0C|NV1C|PCIE
UMASK_TOTAL_REQ_REM 0x00

EVENT_WR_BYTES_LOC 0x02 CNV|NV0C|NV1C|PCIE
UMASK_WR_BYTES_LOC 0x00

EVENT_WR_BYTES_REM 0x03 CNV|NV0C|NV1C|PCIE
UMASK_WR_BYTES_REM 0x00

EVENT_WR_REQ_LOC 0x08 CNV|NV0C|NV1C|PCIE
UMASK_WR_REQ_LOC 0x00

EVENT_WR_REQ_REM 0x09 CNV|NV0C|NV1C|PCIE
UMASK_WR_REQ_REM 0x00


