# =======================================================================================
#
#      Filename:  perfmon_graniterapids_events.txt
#
#      Description:  Event list for Intel Granite Rapids
#
#      Version:   5.4.1
#      Released:  09.12.2024
#
#      Author:   Thomas Gruber (tr), thomas.roehl@googlemail.com
#      Project:  likwid
#
#      Copyright (C) 2024 RRZE, University Erlangen-Nuremberg
#
#      This program is free software: you can redistribute it and/or modify it under
#      the terms of the GNU General Public License as published by the Free Software
#      Foundation, either version 3 of the License, or (at your option) any later
#      version.
#
#      This program is distributed in the hope that it will be useful, but WITHOUT ANY
#      WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
#      PARTICULAR PURPOSE.  See the GNU General Public License for more details.
#
#      You should have received a copy of the GNU General Public License along with
#      this program.  If not, see <http://www.gnu.org/licenses/>.
#
# =======================================================================================

EVENT_TEMP_CORE          0x00   TMP0
UMASK_TEMP_CORE          0x00

EVENT_PWR_PKG_ENERGY          0x02   PWR0
UMASK_PWR_PKG_ENERGY          0x00

EVENT_PWR_PP0_ENERGY          0x01   PWR1
UMASK_PWR_PP0_ENERGY          0x00

EVENT_PWR_PP1_ENERGY          0x04   PWR2
UMASK_PWR_PP1_ENERGY          0x00

EVENT_PWR_DRAM_ENERGY          0x03   PWR3
UMASK_PWR_DRAM_ENERGY          0x00

EVENT_PWR_PLATFORM_ENERGY          0x05   PWR4
UMASK_PWR_PLATFORM_ENERGY          0x00

EVENT_VOLTAGE_CORE          0x00   VTG0
UMASK_VOLTAGE_CORE          0x00

EVENT_INSTR_RETIRED              0x00   FIXC0
UMASK_INSTR_RETIRED_ANY          0x01

EVENT_CPU_CLK_UNHALTED_CORE      0x00   FIXC1
UMASK_CPU_CLK_UNHALTED_CORE      0x02

EVENT_CPU_CLK_UNHALTED_REF       0x00   FIXC2
UMASK_CPU_CLK_UNHALTED_REF       0x03

EVENT_TOPDOWN_SLOTS                0x00   FIXC3
UMASK_TOPDOWN_SLOTS                0x04

EVENT_RETIRING                 0x00 TMA0
UMASK_RETIRING                 0x00

EVENT_BAD_SPECULATION          0x00 TMA1
UMASK_BAD_SPECULATION          0x00

EVENT_FRONTEND_BOUND           0x00 TMA2
UMASK_FRONTEND_BOUND           0x00

EVENT_BACKEND_BOUND            0x00 TMA3
UMASK_BACKEND_BOUND            0x00

EVENT_CPU_CLOCK_UNHALTED                    0x3C   PMC
UMASK_CPU_CLOCK_UNHALTED_THREAD_P           0x00
UMASK_CPU_CLOCK_UNHALTED_REF_XCLK           0x01
UMASK_CPU_CLOCK_UNHALTED_ONE_THREAD_ACTIVE  0x02
UMASK_CPU_CLOCK_UNHALTED_REF_DISTRIBUTED    0x08
# Added by Thomas Gruber: Idea is to count also in halted state
DEFAULT_OPTIONS_CPU_CLOCK_UNHALTED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1
UMASK_CPU_CLOCK_UNHALTED_TOTAL_CYCLES       0x00

# https://github.com/intel/perfmon/blob/main/GNR/events/graniterapids_core.json
# v1.02

EVENT_LD_BLOCKS                 0x03 PMC
UMASK_LD_BLOCKS_ADDRESS_ALIAS   0x04
UMASK_LD_BLOCKS_STORE_FORWARD   0x82
UMASK_LD_BLOCKS_NO_SR           0x88

EVENT_ITLB_MISSES                       0x11 PMC
UMASK_ITLB_MISSES_WALK_COMPLETED_4K     0x02
UMASK_ITLB_MISSES_WALK_COMPLETED_2M_4M  0x04
UMASK_ITLB_MISSES_WALK_COMPLETED        0x0E
DEFAULT_OPTIONS_ITLB_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_ITLB_MISSES_WALK_ACTIVE           0x10
UMASK_ITLB_MISSES_WALK_PENDING          0x10
UMASK_ITLB_MISSES_STLB_HIT              0x20

EVENT_DTLB_LOAD_MISSES                       0x12 PMC
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_4K     0x02
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_2M_4M  0x04
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_1G     0x08
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED        0x0E
DEFAULT_OPTIONS_DTLB_LOAD_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_DTLB_LOAD_MISSES_WALK_ACTIVE           0x10
UMASK_DTLB_LOAD_MISSES_WALK_PENDING          0x10
UMASK_DTLB_LOAD_MISSES_STLB_HIT              0x20

EVENT_DTLB_STORE_MISSES                       0x13 PMC
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_4K     0x02
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_2M_4M  0x04
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_1G     0x08
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED        0x0E
DEFAULT_OPTIONS_DTLB_STORE_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_DTLB_STORE_MISSES_WALK_ACTIVE           0x10
UMASK_DTLB_STORE_MISSES_WALK_PENDING          0x10
UMASK_DTLB_STORE_MISSES_STLB_HIT              0x20

EVENT_OFFCORE_REQUESTS_OUTSTANDING                              0x20 PMC
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD   0x01
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD               0x01
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD   0x02
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_CODE_RD               0x02
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO       0x04
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_RFO                   0x04
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD          0x08
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DATA_RD                      0x08
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD          0x10
UMASK_OFFCORE_REQUESTS_OUTSTANDING_L3_MISS_DEMAND_DATA_RD                      0x10

EVENT_OFFCORE_REQUESTS                              0x21 PMC
UMASK_OFFCORE_REQUESTS_DEMAND_DATA_RD               0x01
UMASK_OFFCORE_REQUESTS_DEMAND_CODE_RD               0x02
UMASK_OFFCORE_REQUESTS_DEMAND_RFO                   0x04
UMASK_OFFCORE_REQUESTS_DATA_RD                      0x08
UMASK_OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_RD       0x10
UMASK_OFFCORE_REQUESTS_ALL_REQUESTS                 0x80

# The only officially released event is L2_TRANS_L2_WB
# All others count something but no guarantees, taken from Haswell micro-architecture (https://perfmon-events.intel.com/haswell.html#)
EVENT_L2_TRANS                  0x23 PMC
UMASK_L2_TRANS_DEMAND_DATA_RD   0x01
UMASK_L2_TRANS_RFO              0x02
UMASK_L2_TRANS_CODE_RD          0x04
UMASK_L2_TRANS_ALL_PF           0x08
UMASK_L2_TRANS_L1D_WB           0x10
UMASK_L2_TRANS_L2_FILL          0x20
UMASK_L2_TRANS_L2_WB            0x40
UMASK_L2_TRANS_ALL_REQUESTS     0x80

EVENT_L2_REQUEST                    0x24 PMC
UMASK_L2_REQUEST_MISS               0x3F
UMASK_L2_REQUEST_HIT                0xDF

EVENT_L2_RQSTS                      0x24 PMC
UMASK_L2_RQSTS_DEMAND_DATA_RD_MISS  0x21
UMASK_L2_RQSTS_RFO_MISS             0x22
UMASK_L2_RQSTS_CODE_RD_MISS         0x24
UMASK_L2_RQSTS_ALL_DEMAND_MISS      0x27
UMASK_L2_RQSTS_SWPF_MISS            0x28
UMASK_L2_RQSTS_HWPF_MISS            0x30
UMASK_L2_RQSTS_MISS                 0x3F
UMASK_L2_RQSTS_DEMAND_DATA_RD_HIT   0xC1
UMASK_L2_RQSTS_RFO_HIT              0xC2
UMASK_L2_RQSTS_CODE_RD_HIT          0xC4
UMASK_L2_RQSTS_SWPF_HIT             0xC8
UMASK_L2_RQSTS_HIT                  0xDF
UMASK_L2_RQSTS_ALL_DEMAND_DATA_RD   0xE1
UMASK_L2_RQSTS_ALL_RFO              0xE2
UMASK_L2_RQSTS_ALL_ALL_CODE_RD      0xE4
UMASK_L2_RQSTS_ALL_DEMAND_REFERENCES 0xE7
UMASK_L2_RQSTS_ALL_HWPF             0xF0
UMASK_L2_RQSTS_REFERENCES           0xFF
UMASK_L2_RQSTS_ALL                  0xFF

EVENT_L2_LINES_IN                   0x25 PMC
UMASK_L2_LINES_IN_ALL               0x1F

EVENT_L2_LINES_OUT                  0x26 PMC
UMASK_L2_LINES_OUT_SILENT           0x01
UMASK_L2_LINES_OUT_NON_SILENT       0x02
UMASK_L2_LINES_OUT_USELESS_HWPF     0x04

EVENT_SQ_MISC                       0x2C PMC
UMASK_SQ_MISC_BUS_LOCK              0x10

EVENT_XQ                            0x2D PMC
UMASK_XQ_FULL_CYCLES                0x01

EVENT_LONGEST_LAT_CACHE             0x2E PMC
UMASK_LONGEST_LAT_CACHE_MISS        0x41
UMASK_LONGEST_LAT_CACHE_REFERENCE   0x4F

EVENT_SW_PREFETCH_ACCESS            0x40 PMC
UMASK_SW_PREFETCH_ACCESS_NTA        0x01
UMASK_SW_PREFETCH_ACCESS_T0         0x02
UMASK_SW_PREFETCH_ACCESS_T1_T2      0x04
UMASK_SW_PREFETCH_ACCESS_PREFETCHW  0x08
UMASK_SW_PREFETCH_ACCESS_ANY        0x0F

EVENT_MEM_LOAD_COMPLETED_L1_MISS_ANY    0x43 PMC
UMASK_MEM_LOAD_COMPLETED_L1_MISS_ANY    0xFD

EVENT_MEM_STORE_RETIRED_L2_HIT          0x44 PMC
UMASK_MEM_STORE_RETIRED_L2_HIT          0x01

EVENT_MEMORY_ACTIVITY                   0x47 PMC
DEFAULT_OPTIONS_MEMORY_ACTIVITY_CYCLES_L1D_MISS EVENT_OPTION_THRESHOLD=0x02
UMASK_MEMORY_ACTIVITY_CYCLES_L1D_MISS   0x02
DEFAULT_OPTIONS_MEMORY_ACTIVITY_STALLS_L1D_MISS EVENT_OPTION_THRESHOLD=0x03
UMASK_MEMORY_ACTIVITY_STALLS_L1D_MISS   0x03
DEFAULT_OPTIONS_MEMORY_ACTIVITY_STALLS_L2_MISS EVENT_OPTION_THRESHOLD=0x05
UMASK_MEMORY_ACTIVITY_STALLS_L2_MISS    0x05
DEFAULT_OPTIONS_MEMORY_ACTIVITY_STALLS_L3_MISS EVENT_OPTION_THRESHOLD=0x09
UMASK_MEMORY_ACTIVITY_STALLS_L3_MISS    0x09

EVENT_L1D_PEND_MISS                     0x48 PMC
UMASK_L1D_PEND_MISS_PENDING             0x01
DEFAULT_OPTIONS_L1D_PEND_MISS_PENDING_CYCLES EVENT_OPTION_THRESHOLD=0x01
UMASK_L1D_PEND_MISS_PENDING_CYCLES      0x01
UMASK_L1D_PEND_MISS_FB_FULL             0x02
DEFAULT_OPTIONS_L1D_PEND_MISS_FB_FULL_PERIODS EVENT_OPTION_THRESHOLD=0x01
UMASK_L1D_PEND_MISS_FB_FULL_PERIODS     0x02
UMASK_L1D_PEND_MISS_L2_STALLS           0x04

EVENT_LOAD_HIT_PREFETCH                 0x4C PMC
UMASK_LOAD_HIT_PREFETCH_SWPF            0x01

EVENT_L1D                               0x51 PMC
UMASK_L1D_REPLACEMENT                   0x01
UMASK_L1D_HWPF_MISS                     0x20

EVENT_BACLEARS_ANY                      0x60 PMC
UMASK_BACLEARS_ANY                      0x01

EVENT_DSB2MITE_SWITCHES_PENALTY_CYCLES  0x61 PMC
UMASK_DSB2MITE_SWITCHES_PENALTY_CYCLES  0x02

EVENT_INST_DECODED_DECODERS             0x75 PMC
UMASK_INST_DECODED_DECODERS             0x01

EVENT_UOPS_DECODED_DEC0_UOPS            0x76 PMC
UMASK_UOPS_DECODED_DEC0_UOPS            0x01

EVENT_IDQ                               0x79 PMC
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_ANY     EVENT_OPTION_THRESHOLD=0x01
UMASK_IDQ_MITE_CYCLES_ANY               0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_OK      EVENT_OPTION_THRESHOLD=0x06
UMASK_IDQ_MITE_CYCLES_OK                0x04
UMASK_IDQ_MITE_UOPS                     0x04
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_ANY      EVENT_OPTION_THRESHOLD=0x01
UMASK_IDQ_DSB_CYCLES_ANY                0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_OK       EVENT_OPTION_THRESHOLD=0x06
UMASK_IDQ_DSB_CYCLES_OK                 0x08
UMASK_IDQ_DSB_UOPS                      0x08
DEFAULT_OPTIONS_IDQ_MS_CYCLES_ANY       EVENT_OPTION_THRESHOLD=0x01
UMASK_IDQ_MS_CYCLES_ANY                 0x08
DEFAULT_OPTIONS_IDQ_MS_SWITCHES         EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1
UMASK_IDQ_MS_SWITCHES                   0x08
UMASK_IDQ_MS_UOPS                       0x08

EVENT_ICACHE_DATA                       0x80 PMC
UMASK_ICACHE_DATA_STALLS                0x04
DEFAULT_OPTIONS_ICACHE_DATA_STALL_PERIODS EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1
UMASK_ICACHE_DATA_STALL_PERIODS         0x04

EVENT_ICACHE_TAG                        0x83 PMC
UMASK_ICACHE_TAG_STALLS                 0x04

EVENT_DECODE                            0x87 PMC
UMASK_DECODE_LCP                        0x01
UMASK_DECODE_MS_BUSY                    0x02

EVENT_IDQ_UOPS_NOT_DELIVERED                            0x9C PMC
UMASK_IDQ_UOPS_NOT_DELIVERED_CORE                       0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE       EVENT_OPTION_THRESHOLD=0x06
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE   0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK       EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK           0x01

EVENT_IDQ_BUBBLES                            0x9C PMC
UMASK_IDQ_BUBBLES_CORE                       0x01
DEFAULT_OPTIONS_IDQ_BUBBLES_CYCLES_0_UOPS_DELIV_CORE       EVENT_OPTION_THRESHOLD=0x06
UMASK_IDQ_BUBBLES_CYCLES_0_UOPS_DELIV_CORE   0x01
DEFAULT_OPTIONS_IDQ_BUBBLES_CYCLES_FE_WAS_OK       EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1
UMASK_IDQ_BUBBLES_CYCLES_FE_WAS_OK           0x01

EVENT_RESOURCE_STALLS                       0xA2 PMC
UMASK_RESOURCE_STALLS_SCOREBOARD            0x02

EVENT_CYCLE_ACTIVITY                        0xA3 PMC
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L2_MISS EVENT_OPTION_THRESHOLD=0x01
UMASK_CYCLE_ACTIVITY_CYCLES_L2_MISS         0x01
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L3_MISS EVENT_OPTION_THRESHOLD=0x02
UMASK_CYCLE_ACTIVITY_CYCLES_L3_MISS         0x02
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_TOTAL EVENT_OPTION_THRESHOLD=0x04
UMASK_CYCLE_ACTIVITY_STALLS_TOTAL           0x04
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L2_MISS EVENT_OPTION_THRESHOLD=0x05
UMASK_CYCLE_ACTIVITY_STALLS_L2_MISS         0x05
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L3_MISS EVENT_OPTION_THRESHOLD=0x06
UMASK_CYCLE_ACTIVITY_STALLS_L3_MISS         0x06
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L1D_MISS EVENT_OPTION_THRESHOLD=0x08
UMASK_CYCLE_ACTIVITY_CYCLES_L1D_MISS         0x08
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L1D_MISS EVENT_OPTION_THRESHOLD=0x0C
UMASK_CYCLE_ACTIVITY_STALLS_L1D_MISS         0x0C
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_MEM_ANY EVENT_OPTION_THRESHOLD=0x10
UMASK_CYCLE_ACTIVITY_CYCLES_MEM_ANY         0x10

EVENT_TOPDOWN                               0x4C PMC
UMASK_TOPDOWN_SLOTS_P                       0x01
UMASK_TOPDOWN_BACKEND_BOUND_SLOTS           0x02
UMASK_TOPDOWN_BAD_SPEC_SLOTS                0x04
UMASK_TOPDOWN_BR_MISPREDICT_SLOTS           0x08
UMASK_TOPDOWN_MEMORY_BOUND_SLOTS            0x10

EVENT_RS                                    0xA5 PMC
UMASK_RS_EMPTY_RESOURCE                     0x01
UMASK_RS_EMPTY                              0x07
DEFAULT_OPTIONS_RS_EMPTY_COUNT       EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1
UMASK_RS_EMPTY_COUNT                        0x07

EVENT_EXE_ACTIVITY                          0xA6 PMC
UMASK_EXE_ACTIVITY_1_PORTS_UTIL             0x02
UMASK_EXE_ACTIVITY_2_PORTS_UTIL             0x04
UMASK_EXE_ACTIVITY_3_PORTS_UTIL             0x08
UMASK_EXE_ACTIVITY_4_PORTS_UTIL             0x10
UMASK_EXE_ACTIVITY_BOUND_ON_LOADS           0x21
UMASK_EXE_ACTIVITY_BOUND_ON_STORES          0x40
UMASK_EXE_ACTIVITY_EXE_BOUND_0_PORTS        0x80
UMASK_EXE_ACTIVITY_2_3_PORTS_UTIL           0xC0

EVENT_LSD                                   0xA8 PMC
DEFAULT_OPTIONS_LSD_CYCLES_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_LSD_CYCLES_ACTIVE                     0x01
DEFAULT_OPTIONS_LSD_CYCLES_OK EVENT_OPTION_THRESHOLD=0x6
UMASK_LSD_CYCLES_OK                         0x01
UMASK_LSD_UOPS                              0x01

EVENT_INT_MISC                              0xAD PMC
UMASK_INT_MISC_RECOVERY_CYCLES              0x01
DEFAULT_OPTIONS_INT_MISC_CLEARS_COUNT       EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1
UMASK_INT_MISC_CLEARS_COUNT                 0x01
UMASK_INT_MISC_UOP_DROPPING                 0x10
UMASK_INT_MISC_MBA_STALLS                   0x20
UMASK_INT_MISC_UNKNOWN_BRANCH_CYCLES        0x40
UMASK_INT_MISC_CLEAR_RESTEER_CYCLES         0x80

EVENT_UOPS_ISSUED                           0xAE PMC
UMASK_UOPS_ISSUED_ANY                       0x01
DEFAULT_OPTIONS_UOPS_ISSUED_CYCLES       EVENT_OPTION_THRESHOLD=0x01
UMASK_UOPS_ISSUED_CYCLES                    0x01

EVENT_ARITH                                 0xD0 PMC
DEFAULT_OPTIONS_ARITH_FPDIV_ACTIVE          EVENT_OPTION_THRESHOLD=0x01
UMASK_ARITH_FPDIV_ACTIVE                    0x01
DEFAULT_OPTIONS_ARITH_FPDIV_COUNT           EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1
UMASK_ARITH_FPDIV_COUNT                     0x01
DEFAULT_OPTIONS_ARITH_IDIV_ACTIVE           EVENT_OPTION_THRESHOLD=0x01
UMASK_ARITH_IDIV_ACTIVE                     0x08
DEFAULT_OPTIONS_ARITH_IDIV_COUNT            EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1
UMASK_ARITH_IDIV_COUNT                      0x08
DEFAULT_OPTIONS_ARITH_DIV_ACTIVE            EVENT_OPTION_THRESHOLD=0x01
UMASK_ARITH_DIV_ACTIVE                      0x09
DEFAULT_OPTIONS_ARITH_DIV_COUNT             EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1
UMASK_ARITH_DIV_COUNT                       0x09

EVENT_UOPS_EXECUTED                         0xB1 PMC
UMASK_UOPS_EXECUTED_THREAD                  0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_1   EVENT_OPTION_THRESHOLD=0x01
UMASK_UOPS_EXECUTED_CYCLES_GE_1             0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_2   EVENT_OPTION_THRESHOLD=0x02
UMASK_UOPS_EXECUTED_CYCLES_GE_2             0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_3   EVENT_OPTION_THRESHOLD=0x03
UMASK_UOPS_EXECUTED_CYCLES_GE_3             0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_4   EVENT_OPTION_THRESHOLD=0x04
UMASK_UOPS_EXECUTED_CYCLES_GE_4             0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_STALLS        EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1
UMASK_UOPS_EXECUTED_STALLS                  0x01
UMASK_UOPS_EXECUTED_CORE                         0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_1   EVENT_OPTION_THRESHOLD=0x01
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_1             0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_2   EVENT_OPTION_THRESHOLD=0x02
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_2             0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_3   EVENT_OPTION_THRESHOLD=0x03
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_3             0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_4   EVENT_OPTION_THRESHOLD=0x04
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_4             0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_STALLS        EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1
UMASK_UOPS_EXECUTED_CORE_STALLS                  0x02
UMASK_UOPS_EXECUTED_X87                     0x10

EVENT_UOPS_DISPATCHED                       0xB2 PMC
UMASK_UOPS_DISPATCHED_PORT_0                0x01
UMASK_UOPS_DISPATCHED_PORT_1                0x02
UMASK_UOPS_DISPATCHED_PORT_2_3_10           0x04
UMASK_UOPS_DISPATCHED_PORT_4_9              0x10
UMASK_UOPS_DISPATCHED_PORT_5_11             0x20
UMASK_UOPS_DISPATCHED_PORT_6                0x40
UMASK_UOPS_DISPATCHED_PORT_7_8              0x80

EVENT_FP_ARITH_DISPATCHED                   0xB3 PMC
UMASK_FP_ARITH_DISPATCHED_PORT_0            0x01
UMASK_FP_ARITH_DISPATCHED_V0                0x01
UMASK_FP_ARITH_DISPATCHED_PORT_1            0x02
UMASK_FP_ARITH_DISPATCHED_V1                0x02
UMASK_FP_ARITH_DISPATCHED_PORT_5            0x04
UMASK_FP_ARITH_DISPATCHED_V2                0x04

EVENT_EXE                                   0xB7 PMC
UMASK_EXE_AMX_BUSY                          0x02

EVENT_INST_RETIRED                          0xC0 PMC
UMASK_INST_RETIRED_ANY_P                    0x00
UMASK_INST_RETIRED_NOP                      0x02
UMASK_INST_RETIRED_REP_ITERATION            0x08
UMASK_INST_RETIRED_MACRO_FUSED              0x10

EVENT_ASSISTS                               0xC1 PMC
UMASK_ASSISTS_FP                            0x02
UMASK_ASSISTS_PAGE_FAULT                    0x08
UMASK_ASSISTS_SSE_AVX_MIX                   0x10
UMASK_ASSISTS_ANY                           0x1B

EVENT_UOPS_RETIRED                          0xC2 PMC
UMASK_UOPS_RETIRED_HEAVY                    0x01
UMASK_UOPS_RETIRED_SLOTS                    0x02
DEFAULT_OPTIONS_UOPS_RETIRED_STALLS         EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_INVERT=0x1
UMASK_UOPS_RETIRED_STALLS                   0x02
DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES         EVENT_OPTION_THRESHOLD=0x01
UMASK_UOPS_RETIRED_CYCLES                   0x02
# Has to be taken alone and required additional filtering. Not added
#UMASK_UOPS_RETIRED_MS                       0x04

EVENT_MACHINE_CLEARS                        0xC3 PMC
DEFAULT_OPTIONS_MACHINE_CLEARS_COUNT        EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=0x1
UMASK_MACHINE_CLEARS_COUNT                  0x01
UMASK_MACHINE_CLEARS_MEMORY_ORDERING        0x02
UMASK_MACHINE_CLEARS_SMC                    0x04

EVENT_BR_INST_RETIRED                       0xC4 PMC
UMASK_BR_INST_RETIRED_ALL_BRANCHES          0x00
UMASK_BR_INST_RETIRED_COND_TAKEN            0x01
UMASK_BR_INST_RETIRED_NEAR_CALL             0x02
UMASK_BR_INST_RETIRED_NEAR_RETURN           0x08
UMASK_BR_INST_RETIRED_COND_NTAKEN           0x10
UMASK_BR_INST_RETIRED_COND                  0x11
UMASK_BR_INST_RETIRED_NEAR_TAKEN            0x20
UMASK_BR_INST_RETIRED_FAR_BRANCH            0x40
UMASK_BR_INST_RETIRED_INDIRECT              0x80

EVENT_BR_MISP_RETIRED                       0xC5 PMC
UMASK_BR_MISP_RETIRED_ALL_BRANCHES          0x00
UMASK_BR_MISP_RETIRED_COND_TAKEN            0x01
UMASK_BR_MISP_RETIRED_INDIRECT_CALL         0x02
UMASK_BR_MISP_RETIRED_RET                   0x08
UMASK_BR_MISP_RETIRED_COND_NTAKEN           0x10
UMASK_BR_MISP_RETIRED_COND                  0x11
UMASK_BR_MISP_RETIRED_NEAR_TAKEN            0x20
UMASK_BR_MISP_RETIRED_COND_TAKEN_COST       0x41
UMASK_BR_MISP_RETIRED_INDIRECT_CALL_COST    0x42
UMASK_BR_MISP_RETIRED_ALL_CALL_COST         0x44
UMASK_BR_MISP_RETIRED_RET_COST              0x48
UMASK_BR_MISP_RETIRED_COND_NTAKEN_COST      0x50
UMASK_BR_MISP_RETIRED_COND_COST             0x51
UMASK_BR_MISP_RETIRED_NEAR_TAKEN_COST       0x60
UMASK_BR_MISP_RETIRED_INDIRECT              0x80
UMASK_BR_MISP_RETIRED_INDIRECT_COST         0xC0

# FRONTEND_RETIRED skipped
#EVENT_FRONTEND_RETIRED                                      0xC6 PMC
#DEFAULT_OPTION_FRONTEND_RETIRED_ANY_DSB_MISS                EVENT_OPTION_MATCH0=0x1
#UMAKS_FRONTEND_RETIRED_ANY_DSB_MISS                         0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_MISP_ANT                    EVENT_OPTION_MATCH0=0x9
#UMAKS_FRONTEND_RETIRED_MISP_ANT                             0x02
#DEFAULT_OPTION_FRONTEND_RETIRED_ANY_ANT                     EVENT_OPTION_MATCH0=0x9
#UMAKS_FRONTEND_RETIRED_ANY_ANT                              0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATE_SWPF                   EVENT_OPTION_MATCH0=0x9
#UMAKS_FRONTEND_RETIRED_LATE_SWPF                            0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_DSB_MISS                    EVENT_OPTION_MATCH0=0x11
#UMAKS_FRONTEND_RETIRED_DSB_MISS                             0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_ITLB_MISS                   EVENT_OPTION_MATCH0=0x14
#UMAKS_FRONTEND_RETIRED_ITLB_MISS                            0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_L1I_MISS                    EVENT_OPTION_MATCH0=0x12
#UMAKS_FRONTEND_RETIRED_L1I_MISS                             0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_L2_MISS                     EVENT_OPTION_MATCH0=0x13
#UMAKS_FRONTEND_RETIRED_L2_MISS                              0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_STLB_MISS                   EVENT_OPTION_MATCH0=0x15
#UMAKS_FRONTEND_RETIRED_STLB_MISS                            0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_MS_FLOWS                    EVENT_OPTION_MATCH0=0x8
#UMAKS_FRONTEND_RETIRED_MS_FLOWS                             0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_UNKNOWN_BRANCH              EVENT_OPTION_MATCH0=0x17
#UMAKS_FRONTEND_RETIRED_UNKNOWN_BRANCH                       0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_1                EVENT_OPTION_MATCH0=0x600106
#UMAKS_FRONTEND_RETIRED_LATENCY_GE_1                         0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_2                EVENT_OPTION_MATCH0=0x600206
#UMAKS_FRONTEND_RETIRED_LATENCY_GE_2                         0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1   EVENT_OPTION_MATCH0=0x100206
#UMASK_FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1            0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_4                EVENT_OPTION_MATCH0=0x600406
#UMAKS_FRONTEND_RETIRED_LATENCY_GE_4                         0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_8                EVENT_OPTION_MATCH0=0x600806
#UMAKS_FRONTEND_RETIRED_LATENCY_GE_8                         0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_16               EVENT_OPTION_MATCH0=0x601006
#UMAKS_FRONTEND_RETIRED_LATENCY_GE_16                        0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_32               EVENT_OPTION_MATCH0=0x602006
#UMAKS_FRONTEND_RETIRED_LATENCY_GE_32                        0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_64               EVENT_OPTION_MATCH0=0x604006
#UMAKS_FRONTEND_RETIRED_LATENCY_GE_64                        0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_128              EVENT_OPTION_MATCH0=0x608006
#UMAKS_FRONTEND_RETIRED_LATENCY_GE_128                       0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_256              EVENT_OPTION_MATCH0=0x610006
#UMAKS_FRONTEND_RETIRED_LATENCY_GE_256                       0x03
#DEFAULT_OPTION_FRONTEND_RETIRED_LATENCY_GE_512              EVENT_OPTION_MATCH0=0x620006
#UMAKS_FRONTEND_RETIRED_LATENCY_GE_512                       0x03

EVENT_FP_ARITH_INST_RETIRED                         0xC7 PMC
UMASK_FP_ARITH_INST_RETIRED_SCALAR_DOUBLE           0x01
UMASK_FP_ARITH_INST_RETIRED_SCALAR_SINGLE           0x02
UMASK_FP_ARITH_INST_RETIRED_SCALAR                  0x03
UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE      0x04
UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_SINGLE      0x08
UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE      0x10
UMASK_FP_ARITH_INST_RETIRED_4_FLOPS                 0x18
UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE      0x20
UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_DOUBLE      0x40
UMASK_FP_ARITH_INST_RETIRED_8_FLOPS                 0x60
UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_SINGLE      0x80
UMASK_FP_ARITH_INST_RETIRED_VECTOR                  0xFC

EVENT_FP_ARITH_INST_RETIRED2                        0xCF PMC
UMASK_FP_ARITH_INST_RETIRED2_SCALAR_HALF            0x01
UMASK_FP_ARITH_INST_RETIRED2_COMPLEX_SCALAR_HALF    0x02
UMASK_FP_ARITH_INST_RETIRED2_SCALAR                 0x03
UMASK_FP_ARITH_INST_RETIRED2_128B_PACKED_HALF       0x04
UMASK_FP_ARITH_INST_RETIRED2_256B_PACKED_HALF       0x08
UMASK_FP_ARITH_INST_RETIRED2_512B_PACKED_HALF       0x10
UMASK_FP_ARITH_INST_RETIRED2_VECTOR                 0x1C

EVENT_LBR_INSERTS                                   0xCC PMC
UMASK_LBR_INSERTS_LBR_INSERTS                       0x20

#MEM_TRANS_RETIRED skipped

EVENT_MEM_INST_RETIRED                              0xD0 PMC
UMASK_MEM_INST_RETIRED_STLB_HIT_LOADS               0x09
UMASK_MEM_INST_RETIRED_STLB_HIT_STORES              0x0A
UMASK_MEM_INST_RETIRED_STLB_MISS_LOADS              0x11
UMASK_MEM_INST_RETIRED_STLB_MISS_STORES             0x12
UMASK_MEM_INST_RETIRED_LOCK_LOADS                   0x21
UMASK_MEM_INST_RETIRED_SPLIT_LOADS                  0x41
UMASK_MEM_INST_RETIRED_SPLIT_STORES                 0x42
UMASK_MEM_INST_RETIRED_ALL_LOADS                    0x81
UMASK_MEM_INST_RETIRED_ALL_STORES                   0x82
UMASK_MEM_INST_RETIRED_ANY                          0x83

EVENT_MEM_LOAD_RETIRED                              0xD1 PMC
UMASK_MEM_LOAD_RETIRED_L1_HIT                       0x01
UMASK_MEM_LOAD_RETIRED_L2_HIT                       0x02
UMASK_MEM_LOAD_RETIRED_L3_HIT                       0x04
UMASK_MEM_LOAD_RETIRED_L1_MISS                      0x08
UMASK_MEM_LOAD_RETIRED_L2_MISS                      0x10
UMASK_MEM_LOAD_RETIRED_L3_MISS                      0x20
UMASK_MEM_LOAD_RETIRED_FB_HIT                       0x40

EVENT_MEM_LOAD_L3_HIT_RETIRED                       0xD2 PMC
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_MISS             0x01
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_NO_FWD           0x02
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_FWD              0x04
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_NONE             0x08

EVENT_MEM_LOAD_L3_MISS_RETIRED                      0xD3 PMC
UMASK_MEM_LOAD_L3_MISS_RETIRED_LOCAL_DRAM           0x01
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_DRAM          0x02
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_HITM          0x04
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_FWD           0x08

EVENT_MEM_LOAD_MISC_RETIRED_UC                      0xD4 PMC
UMASK_MEM_LOAD_MISC_RETIRED_UC                      0x04

EVENT_MISC2_RETIRED_LFENCE                          0xE0 PMC
UMASK_MISC2_RETIRED_LFENCE                          0x20

EVENT_MEM_UOP_RETIRED_ANY                           0xE5 PMC
UMASK_MEM_UOP_RETIRED_ANY                           0x03

EVENT_INT_VEC_RETIRED                               0xE7 PMC
UMASK_INT_VEC_RETIRED_ADD_128                       0x03
UMASK_INT_VEC_RETIRED_ADD_256                       0x0C
UMASK_INT_VEC_RETIRED_VNNI_128                      0x10
UMASK_INT_VEC_RETIRED_128BIT                        0x13
UMASK_INT_VEC_RETIRED_VNNI_256                      0x20
UMASK_INT_VEC_RETIRED_SHUFFLES                      0x40
UMASK_INT_VEC_RETIRED_MUL_256                       0x80
UMASK_INT_VEC_RETIRED_256BIT                        0xAC

EVENT_CPU_CLK_UNHALTED                              0xEC PMC
UMASK_CPU_CLK_UNHALTED_DISTRIBUTED                  0x02
UMASK_CPU_CLK_UNHALTED_C01                          0x10
UMASK_CPU_CLK_UNHALTED_C02                          0x20
UMASK_CPU_CLK_UNHALTED_PAUSE                        0x40
DEFAULT_OPTIONS_CPU_CLK_UNHALTED_PAUSE_INST         EVENT_OPTION_THRESHOLD=0x01
UMASK_CPU_CLK_UNHALTED_PAUSE_INST                   0x40
UMASK_CPU_CLK_UNHALTED_C0_WAIT                      0x70

EVENT_OFFCORE_RESPONSE_0                            0x2A PMC
OPTIONS_OFFCORE_RESPONSE_0_OPTIONS                  EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_MATCH1_MASK
UMASK_OFFCORE_RESPONSE_0_OPTIONS                    0x01 0xFF 0xFF

EVENT_OFFCORE_RESPONSE_1                            0x2B PMC
OPTIONS_OFFCORE_RESPONSE_1_OPTIONS                  EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_MATCH1_MASK
UMASK_OFFCORE_RESPONSE_1_OPTIONS                    0x01 0xFF 0xFF

# https://github.com/intel/perfmon/blob/main/GNR/events/graniterapids_uncore_experimental.json
# https://github.com/intel/perfmon/blob/main/GNR/events/graniterapids_uncore.json
# v1.03

#######################################################
#              UBOX == UBOX                           #
#######################################################

EVENT_UNCORE_CLOCKTICKS         0x01 UBOX
UMASK_UNCORE_CLOCKTICKS         0x00

#######################################################
#                   MBOX == iMC                       #
#######################################################

EVENT_MBOX_CLOCKTICKS           0x01 MBOX
UMASK_MBOX_CLOCKTICKS           0x00

EVENT_ACT_COUNT                 0x02 MBOX
UMASK_ACT_COUNT_RD              0xF1
UMASK_ACT_COUNT_WR              0xF2
UMASK_ACT_COUNT_UFILL           0xF4
UMASK_ACT_COUNT_ALL             0xF7

EVENT_PRE_COUNT                 0x03 MBOX
UMASK_PRE_COUNT_RD              0xF1
UMASK_PRE_COUNT_WR              0xF2
UMASK_PRE_COUNT_UFILL           0xF4
UMASK_PRE_COUNT_PGT             0xF8
UMASK_PRE_COUNT_ALL             0xFF

EVENT_CAS_COUNT_SCH0                0x05 MBOX
UMASK_CAS_COUNT_SCH0_RD_REG         0xC1
UMASK_CAS_COUNT_SCH0_RD_UNDERFILL   0xC4
UMASK_CAS_COUNT_SCH0_RD             0xCF
UMASK_CAS_COUNT_SCH0_WR_PRE         0xE0
UMASK_CAS_COUNT_SCH0_WR_NONPRE      0xD0
UMASK_CAS_COUNT_SCH0_WR             0xF0
UMASK_CAS_COUNT_SCH0_ALL            0xFF

EVENT_CAS_COUNT_SCH1                0x06 MBOX
UMASK_CAS_COUNT_SCH1_RD_REG         0xC1
UMASK_CAS_COUNT_SCH1_RD_UNDERFILL   0xC4
UMASK_CAS_COUNT_SCH1_RD             0xCF
UMASK_CAS_COUNT_SCH1_WR_PRE         0xE0
UMASK_CAS_COUNT_SCH1_WR_NONPRE      0xD0
UMASK_CAS_COUNT_SCH1_WR             0xF0
UMASK_CAS_COUNT_SCH1_ALL            0xFF

EVENT_RPQ_INSERTS                   0x10 MBOX
UMASK_RPQ_INSERTS_SCH0_PCH0         0x10
UMASK_RPQ_INSERTS_SCH0_PCH1         0x20
# Added by Thomas Gruber
UMASK_RPQ_INSERTS_SCH0_ANY          0x30
UMASK_RPQ_INSERTS_SCH1_PCH0         0x40
UMASK_RPQ_INSERTS_SCH1_PCH1         0x80
# Added by Thomas Gruber
UMASK_RPQ_INSERTS_SCH1_ANY          0xC0
UMASK_RPQ_INSERTS_ANY_ANY           0xF0

EVENT_WPQ_INSERTS                   0x22 MBOX
UMASK_WPQ_INSERTS_SCH0_PCH0         0x10
UMASK_WPQ_INSERTS_SCH0_PCH1         0x20
# Added by Thomas Gruber
UMASK_WPQ_INSERTS_SCH0_ANY          0x30
UMASK_WPQ_INSERTS_SCH1_PCH0         0x40
UMASK_WPQ_INSERTS_SCH1_PCH1         0x80
# Added by Thomas Gruber
UMASK_WPQ_INSERTS_SCH1_ANY          0xC0
UMASK_WPQ_INSERTS_ANY_ANY           0xF0

EVENT_RDB_INSERTS                   0x17 MBOX
UMASK_RDB_INSERTS_SCH0              0x40
UMASK_RDB_INSERTS_SCH1              0x80

EVENT_RDB_OCCUPANCY_SCH0            0x1A MBOX
UMASK_RDB_OCCUPANCY_SCH0            0x00

EVENT_RDB_OCCUPANCY_SCH1            0x1B MBOX
UMASK_RDB_OCCUPANCY_SCH1            0x00

EVENT_RPQ_OCCUPANCY_SCH0_PCH0       0x80 MBOX
UMASK_RPQ_OCCUPANCY_SCH0_PCH0       0x00

EVENT_RPQ_OCCUPANCY_SCH0_PCH1       0x81 MBOX
UMASK_RPQ_OCCUPANCY_SCH0_PCH1       0x00

EVENT_RPQ_OCCUPANCY_SCH1_PCH0       0x82 MBOX
UMASK_RPQ_OCCUPANCY_SCH1_PCH0       0x00

EVENT_RPQ_OCCUPANCY_SCH1_PCH1       0x83 MBOX
UMASK_RPQ_OCCUPANCY_SCH1_PCH1       0x00

EVENT_WPQ_OCCUPANCY_SCH0_PCH0       0x84 MBOX
UMASK_WPQ_OCCUPANCY_SCH0_PCH0       0x00

EVENT_WPQ_OCCUPANCY_SCH0_PCH1       0x85 MBOX
UMASK_WPQ_OCCUPANCY_SCH0_PCH1       0x00

EVENT_WPQ_OCCUPANCY_SCH1_PCH0       0x86 MBOX
UMASK_WPQ_OCCUPANCY_SCH1_PCH0       0x00

EVENT_WPQ_OCCUPANCY_SCH1_PCH1       0x87 MBOX
UMASK_WPQ_OCCUPANCY_SCH1_PCH1       0x00

EVENT_POWERDOWN_CYCLES              0x47 MBOX
UMASK_POWERDOWN_CYCLES_SCH0_RANK0   0x01
UMASK_POWERDOWN_CYCLES_SCH0_RANK1   0x02
UMASK_POWERDOWN_CYCLES_SCH0_RANK2   0x04
UMASK_POWERDOWN_CYCLES_SCH0_RANK3   0x08
UMASK_POWERDOWN_CYCLES_SCH1_RANK0   0x10
UMASK_POWERDOWN_CYCLES_SCH1_RANK1   0x20
UMASK_POWERDOWN_CYCLES_SCH1_RANK2   0x40
UMASK_POWERDOWN_CYCLES_SCH1_RANK3   0x80
#Added by T.Gruber
UMASK_POWERDOWN_CYCLES_SCH0_ANYRANK 0x0F
UMASK_POWERDOWN_CYCLES_SCH1_ANYRANK 0xF0
UMASK_POWERDOWN_CYCLES_ANY          0xFF

EVENT_POWER_CHANNEL_PPD_CYCLES      0x88 MBOX
UMASK_POWER_CHANNEL_PPD_CYCLES      0x00

EVENT_SELF_REFRESH                      0x43 MBOX
UMASK_SELF_REFRESH_ENTER_SUCCESS_CYCLES 0x01
UMASK_SELF_REFRESH_ENTER_SUCCESS        0x02

#EVENT_MBOX_CLOCKTICKS_DCLK                   0x00 MBOX0FIX|MBOX1FIX|MBOX2FIX|MBOX3FIX|MBOX4FIX|MBOX5FIX|MBOX6FIX|MBOX7FIX|MBOX8FIX|MBOX9FIX|MBOX10FIX|MBOX11FIX|MBOX12FIX|MBOX13FIX|MBOX14FIX|MBOX15FIX
#UMASK_MBOX_CLOCKTICKS_DCLK                   0x00

#######################################################
#                   MDF == MDF                        #
#######################################################

EVENT_MDF_CLOCKTICKS                0x01 MDF
UMASK_MDF_CLOCKTICKS                0x00

EVENT_RXR_INSERTS                   0x12 MDF
UMASK_RXR_INSERTS_AD_BNC            0x01
UMASK_RXR_INSERTS_AK                0x02
UMASK_RXR_INSERTS_BL_BNC            0x04
UMASK_RXR_INSERTS_IV                0x08
UMASK_RXR_INSERTS_AD_CRD            0x10
UMASK_RXR_INSERTS_BL_CRD            0x20

EVENT_RXR_OCCUPANCY                   0x13 MDF
UMASK_RXR_OCCUPANCY_AD_BNC            0x01
UMASK_RXR_OCCUPANCY_AK                0x02
UMASK_RXR_OCCUPANCY_BL_BNC            0x04
UMASK_RXR_OCCUPANCY_IV                0x08
UMASK_RXR_OCCUPANCY_AD_CRD            0x10
UMASK_RXR_OCCUPANCY_BL_CRD            0x20

EVENT_RXR_BYPASS                   0x14 MDF
UMASK_RXR_BYPASS_AD_BNC            0x01
UMASK_RXR_BYPASS_AK                0x02
UMASK_RXR_BYPASS_BL_BNC            0x04
UMASK_RXR_BYPASS_IV                0x08
UMASK_RXR_BYPASS_AD_CRD            0x10
UMASK_RXR_BYPASS_BL_CRD            0x20

EVENT_TXR_INSERTS                   0x1C MDF
UMASK_TXR_INSERTS_AD_BNC            0x01
UMASK_TXR_INSERTS_AK                0x02
UMASK_TXR_INSERTS_BL_BNC            0x04
UMASK_TXR_INSERTS_IV                0x08
UMASK_TXR_INSERTS_AD_CRD            0x10
UMASK_TXR_INSERTS_BL_CRD            0x20

EVENT_TXR_OCCUPANCY                   0x1D MDF
UMASK_TXR_OCCUPANCY_AD_BNC            0x01
UMASK_TXR_OCCUPANCY_AK                0x02
UMASK_TXR_OCCUPANCY_BL_BNC            0x04
UMASK_TXR_OCCUPANCY_IV                0x08
UMASK_TXR_OCCUPANCY_AD_CRD            0x10
UMASK_TXR_OCCUPANCY_BL_CRD            0x20

EVENT_TXR_BYPASS                   0x1E MDF
UMASK_TXR_BYPASS_AD_BNC            0x01
UMASK_TXR_BYPASS_AK                0x02
UMASK_TXR_BYPASS_BL_BNC            0x04
UMASK_TXR_BYPASS_IV                0x08
UMASK_TXR_BYPASS_AD_CRD            0x10
UMASK_TXR_BYPASS_BL_CRD            0x20

#######################################################
#                   UPI == UPI LL                     #
#######################################################

EVENT_UPI_CLOCKTICKS                0x01 UPI
UMASK_UPI_CLOCKTICKS                0x00

EVENT_TXL_FLITS                         0x02 UPI
UMASK_TXL_FLITS_SLOT0                   0x01
UMASK_TXL_FLITS_SLOT1                   0x02
UMASK_TXL_FLITS_SLOT2                   0x04
UMASK_TXL_FLITS_DATA                    0x08
UMASK_TXL_FLITS_LLCRD                   0x10
UMASK_TXL_FLITS_NULL                    0x20
UMASK_TXL_FLITS_LLCTRL                  0x40
UMASK_TXL_FLITS_PROTHDR                 0x80
UMASK_TXL_FLITS_IDLE                    0x47
UMASK_TXL_FLITS_ALL_PROTHDR                        0x87
UMASK_TXL_FLITS_ALL_LLCTRL                         0x47
UMASK_TXL_FLITS_ALL_LLCRD                          0x17
# Added by T. Gruber
UMASK_TXL_FLITS_DATA_SLOT0              0x09
# Added by T. Gruber
UMASK_TXL_FLITS_DATA_SLOT1              0x0A
# Added by T. Gruber
UMASK_TXL_FLITS_DATA_SLOT2              0x0C
# Added by T. Gruber
UMASK_TXL_FLITS_ALL_DATA                0x0F
UMASK_TXL_FLITS_ALL_NULL                0x27
UMASK_TXL_FLITS_NON_DATA                0x97

EVENT_RXL_FLITS                         0x03 UPI
UMASK_RXL_FLITS_SLOT0                   0x01
UMASK_RXL_FLITS_SLOT1                   0x02
UMASK_RXL_FLITS_SLOT2                   0x04
UMASK_RXL_FLITS_DATA                    0x08
UMASK_RXL_FLITS_LLCRD                   0x10
UMASK_RXL_FLITS_NULL                    0x20
UMASK_RXL_FLITS_LLCTRL                  0x40
UMASK_RXL_FLITS_PROTHDR                 0x80
UMASK_RXL_FLITS_IDLE                    0x47
# Added by T. Gruber
UMASK_RXL_FLITS_DATA_SLOT0              0x09
# Added by T. Gruber
UMASK_RXL_FLITS_DATA_SLOT1              0x0A
# Added by T. Gruber
UMASK_RXL_FLITS_DATA_SLOT2              0x0C
UMASK_RXL_FLITS_ALL_DATA                0x0F
UMASK_RXL_FLITS_NON_DATA                0x97

EVENT_TXL_BASIC_HDR_MATCH                   0x04 UPI
OPTIONS_TXL_BASIC_HDR_MATCH                 EVENT_OPTION_MATCH0_MASK
UMASK_TXL_BASIC_HDR_MATCH_REQ               0x08
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_REQ_OPC EVENT_OPTION_MATCH0=0x01
UMASK_TXL_BASIC_HDR_MATCH_REQ_OPC           0x08
UMASK_TXL_BASIC_HDR_MATCH_SNP               0x09
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_SNP_OPC EVENT_OPTION_MATCH0=0x01
UMASK_TXL_BASIC_HDR_MATCH_SNP_OPC           0x09
UMASK_TXL_BASIC_HDR_MATCH_RSP_NODATA        0x0A
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSP_NODATA_OPC EVENT_OPTION_MATCH0=0x01
UMASK_TXL_BASIC_HDR_MATCH_RSP_NODATA_OPC    0x0A
UMASK_TXL_BASIC_HDR_MATCH_RSP_DATA          0x0C
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSP_DATA_OPC EVENT_OPTION_MATCH0=0x01
UMASK_TXL_BASIC_HDR_MATCH_RSP_DATA_OPC      0x0C
UMASK_TXL_BASIC_HDR_MATCH_WB                0x0D
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_WB_OPC EVENT_OPTION_MATCH0=0x01
UMASK_TXL_BASIC_HDR_MATCH_WB_OPC            0x0D
UMASK_TXL_BASIC_HDR_MATCH_NCB               0x0E
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_NCB_OPC EVENT_OPTION_MATCH0=0x01
UMASK_TXL_BASIC_HDR_MATCH_NCB_OPC           0x0E
UMASK_TXL_BASIC_HDR_MATCH_NCS               0x0F
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_NCS_OPC EVENT_OPTION_MATCH0=0x01
UMASK_TXL_BASIC_HDR_MATCH_NCS_OPC           0x0F
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSPI EVENT_OPTION_MATCH0=0x01
UMASK_TXL_BASIC_HDR_MATCH_RSPI              0x2A
DEFAULT_OPTIONS_TXL_BASIC_HDR_MATCH_RSPCNFLT EVENT_OPTION_MATCH0=0x01
UMASK_TXL_BASIC_HDR_MATCH_RSPCNFLT          0xAA

EVENT_RXL_BASIC_HDR_MATCH                   0x05 UPI
OPTIONS_RXL_BASIC_HDR_MATCH                 EVENT_OPTION_MATCH0_MASK
UMASK_RXL_BASIC_HDR_MATCH_REQ               0x08
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_REQ_OPC EVENT_OPTION_MATCH0=0x01
UMASK_RXL_BASIC_HDR_MATCH_REQ_OPC           0x08
UMASK_RXL_BASIC_HDR_MATCH_SNP               0x09
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_SNP_OPC EVENT_OPTION_MATCH0=0x01
UMASK_RXL_BASIC_HDR_MATCH_SNP_OPC           0x09
UMASK_RXL_BASIC_HDR_MATCH_RSP_NODATA        0x0A
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSP_NODATA_OPC EVENT_OPTION_MATCH0=0x01
UMASK_RXL_BASIC_HDR_MATCH_RSP_NODATA_OPC    0x0A
UMASK_RXL_BASIC_HDR_MATCH_RSP_DATA          0x0C
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSP_DATA_OPC EVENT_OPTION_MATCH0=0x01
UMASK_RXL_BASIC_HDR_MATCH_RSP_DATA_OPC      0x0C
UMASK_RXL_BASIC_HDR_MATCH_WB                0x0D
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_WB_OPC EVENT_OPTION_MATCH0=0x01
UMASK_RXL_BASIC_HDR_MATCH_WB_OPC            0x0D
UMASK_RXL_BASIC_HDR_MATCH_NCB               0x0E
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_NCB_OPC EVENT_OPTION_MATCH0=0x01
UMASK_RXL_BASIC_HDR_MATCH_NCB_OPC           0x0E
UMASK_RXL_BASIC_HDR_MATCH_NCS               0x0F
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_NCS_OPC EVENT_OPTION_MATCH0=0x01
UMASK_RXL_BASIC_HDR_MATCH_NCS_OPC           0x0F
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSPI EVENT_OPTION_MATCH0=0x01
UMASK_RXL_BASIC_HDR_MATCH_RSPI              0x2A
DEFAULT_OPTIONS_RXL_BASIC_HDR_MATCH_RSPCNFLT EVENT_OPTION_MATCH0=0x01
UMASK_RXL_BASIC_HDR_MATCH_RSPCNFLT          0xAA

EVENT_L1_POWER_CYCLES                       0x21 UPI
UMASK_L1_POWER_CYCLES                       0x00

EVENT_TXL0P_POWER_CYCLES                    0x27 UPI
UMASK_TXL0P_POWER_CYCLES                    0x00

EVENT_TXL0P_POWER_CYCLES_LL_ENTER           0x28 UPI
EVENT_TXL0P_POWER_CYCLES_LL_ENTER           0x00

EVENT_TXL0P_POWER_CYCLES_M3_EXIT            0x29 UPI
UMASK_TXL0P_POWER_CYCLES_M3_EXIT            0x00

EVENT_RXL_INSERTS                           0x30 UPI
UMASK_RXL_INSERTS_SLOT0                     0x01
UMASK_RXL_INSERTS_SLOT1                     0x02
UMASK_RXL_INSERTS_SLOT2                     0x04

EVENT_RXL_OCCUPANCY                           0x32 UPI
UMASK_RXL_OCCUPANCY_SLOT0                     0x01
UMASK_RXL_OCCUPANCY_SLOT1                     0x02
UMASK_RXL_OCCUPANCY_SLOT2                     0x04

EVENT_TXL_INSERTS                           0x40 UPI
UMASK_TXL_INSERTS                           0x00

EVENT_TXL_OCCUPANCY                         0x42 UPI
UMASK_TXL_OCCUPANCY                         0x00

#######################################################
#              CBOX == CHA                            #
#######################################################

EVENT_CBOX_CLOCKTICKS                   0x01 CBOX
UMASK_CBOX_CLOCKTICKS                   0x00

EVENT_CHA_CLOCKTICKS                    0x01 CBOX
UMASK_CHA_CLOCKTICKS                    0x00

EVENT_DISTRESS_ASSERTED                 0x59 CBOX
UMASK_DISTRESS_ASSERTED_DPT_IRQ         0x01
UMASK_DISTRESS_ASSERTED_DPT_TOR         0x02
UMASK_DISTRESS_ASSERTED_DPT_ANY         0x03

EVENT_TOR_INSERTS                                       0x35 CBOX
OPTIONS_TOR_INSERTS                                     EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_TOR_INSERTS_LLC_OR_SF_EVICTIONS         EVENT_OPTION_MATCH0=0x00C001FF
UMASK_TOR_INSERTS_LLC_OR_SF_EVICTIONS                   0x02
DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOMCACHENEAR_LOCAL      EVENT_OPTION_MATCH0=0x00CD42FF
UMASK_TOR_INSERTS_IO_ITOMCACHENEAR_LOCAL                0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOMCACHENEAR_REMOTE     EVENT_OPTION_MATCH0=0x00CD437F
UMASK_TOR_INSERTS_IO_ITOMCACHENEAR_REMOTE               0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOM_LOCAL               EVENT_OPTION_MATCH0=0x00CC42FF
UMASK_TOR_INSERTS_IO_ITOM_LOCAL                         0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_ITOM_REMOTE              EVENT_OPTION_MATCH0=0x00CC437F
UMASK_TOR_INSERTS_IO_ITOM_REMOTE                        0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_PCIRDCUR_LOCAL           EVENT_OPTION_MATCH0=0x00C8F2FF
UMASK_TOR_INSERTS_IO_PCIRDCUR_LOCAL                     0x04
DEFAULT_OPTIONS_TOR_INSERTS_IO_PCIRDCUR_REMOTE          EVENT_OPTION_MATCH0=0x00C8F37F
UMASK_TOR_INSERTS_IO_PCIRDCUR_REMOTE                    0x04


EVENT_TOR_OCCUPANCY                                     0x36 CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0|CBOX24C0|CBOX25C0|CBOX26C0|CBOX27C0|CBOX28C0|CBOX29C0|CBOX30C0|CBOX31C0|CBOX32C0|CBOX33C0|CBOX34C0|CBOX35C0|CBOX36C0|CBOX37C0|CBOX38C0|CBOX39C0|CBOX40C0|CBOX41C0|CBOX42C0|CBOX43C0|CBOX44C0|CBOX45C0|CBOX46C0|CBOX47C0|CBOX48C0|CBOX49C0|CBOX50C0|CBOX51C0|CBOX52C0|CBOX53C0|CBOX54C0|CBOX55C0|CBOX56C0|CBOX57C0|CBOX58C0|CBOX59C0|CBOX60C0|CBOX61C0|CBOX62C0|CBOX63C0|CBOX64C0|CBOX65C0|CBOX66C0|CBOX67C0|CBOX68C0|CBOX69C0|CBOX70C0|CBOX71C0|CBOX72C0|CBOX73C0|CBOX74C0|CBOX75C0|CBOX76C0|CBOX77C0|CBOX78C0|CBOX79C0|CBOX80C0|CBOX81C0|CBOX82C0|CBOX83C0|CBOX84C0|CBOX85C0|CBOX86C0|CBOX87C0|CBOX88C0|CBOX89C0|CBOX90C0|CBOX91C0|CBOX92C0|CBOX93C0|CBOX94C0|CBOX95C0|CBOX96C0|CBOX97C0|CBOX98C0|CBOX99C0|CBOX100C0|CBOX101C0|CBOX102C0|CBOX103C0|CBOX104C0|CBOX105C0|CBOX106C0|CBOX107C0|CBOX108C0|CBOX109C0|CBOX110C0|CBOX111C0|CBOX112C0|CBOX113C0|CBOX114C0|CBOX115C0|CBOX116C0|CBOX117C0|CBOX118C0|CBOX119C0|CBOX120C0|CBOX121C0|CBOX122C0|CBOX123C0|CBOX124C0|CBOX125C0
OPTIONS_TOR_OCCUPANCY                                   EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_PCIRDCUR_REMOTE   EVENT_OPTION_MATCH0=0x00C8F37E
UMASK_TOR_OCCUPANCY_IO_MISS_PCIRDCUR_REMOTE             0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_PCIRDCUR_LOCAL    EVENT_OPTION_MATCH0=0x00C8F2FE
UMASK_TOR_OCCUPANCY_IO_MISS_PCIRDCUR_LOCAL              0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_ITOM_REMOTE       EVENT_OPTION_MATCH0=0x00CC437E
UMASK_TOR_OCCUPANCY_IO_MISS_ITOM_REMOTE                 0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_ITOM_LOCAL        EVENT_OPTION_MATCH0=0x00CC42FE
UMASK_TOR_OCCUPANCY_IO_MISS_ITOM_LOCAL                  0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_ITOMCACHENEAR_REMOTE        EVENT_OPTION_MATCH0=0x00CD437E
UMASK_TOR_OCCUPANCY_IO_MISS_ITOMCACHENEAR_REMOTE                  0x04
DEFAULT_OPTIONS_TOR_OCCUPANCY_IO_MISS_ITOMCACHENEAR_LOCAL         EVENT_OPTION_MATCH0=0x00CD42FE
UMASK_TOR_OCCUPANCY_IO_MISS_ITOMCACHENEAR_LOCAL                   0x04


EVENT_LLC_VICTIMS                                       0x37 CBOX
OPTIONS_LLC_VICTIMS                                     EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_M                     EVENT_OPTION_MATCH0=0x00000020
UMASK_LLC_VICTIMS_LOCAL_M                               0x01
DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_E                     EVENT_OPTION_MATCH0=0x00000020
UMASK_LLC_VICTIMS_LOCAL_E                               0x02
DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_S                     EVENT_OPTION_MATCH0=0x00000020
UMASK_LLC_VICTIMS_LOCAL_S                               0x04
DEFAULT_OPTIONS_LLC_VICTIMS_LOCAL_F                     EVENT_OPTION_MATCH0=0x00000020
UMASK_LLC_VICTIMS_LOCAL_F                               0x08
DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_M                    EVENT_OPTION_MATCH0=0x00000080
UMASK_LLC_VICTIMS_REMOTE_M                              0x01
DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_E                    EVENT_OPTION_MATCH0=0x00000080
UMASK_LLC_VICTIMS_REMOTE_E                              0x02
DEFAULT_OPTIONS_LLC_VICTIMS_REMOTE_S                    EVENT_OPTION_MATCH0=0x00000080
UMASK_LLC_VICTIMS_REMOTE_S                              0x04

EVENT_REMOTE_SF                         0x69 CBOX
UMASK_REMOTE_SF_HIT                     0x01
UMASK_REMOTE_SF_HIT_EXCLUSIVE           0x02
UMASK_REMOTE_SF_MISS                    0x04
UMASK_REMOTE_SF_ALLOC_SHARED            0x08
UMASK_REMOTE_SF_ALLOC_EXCLUSIVE         0x10
UMASK_REMOTE_SF_DEALLOC_EVCTCLN         0x40
UMASK_REMOTE_SF_UPDATE_SHARED           0x80
OPTIONS_REMOTE_SF_UPDATE_EXCLUSIVE      EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_REMOTE_SF_UPDATE_EXCLUSIVE EVENT_OPTION_MATCH0=0x00000001
UMASK_REMOTE_SF_UPDATE_EXCLUSIVE        0x00
OPTIONS_REMOTE_SF_VICTIM_SHARED         EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_REMOTE_SF_VICTIM_SHARED EVENT_OPTION_MATCH0=0x00000002
UMASK_REMOTE_SF_VICTIM_SHARED           0x00
OPTIONS_REMOTE_SF_VICTIM_EXCLUSIVE      EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_REMOTE_SF_VICTIM_EXCLUSIVE EVENT_OPTION_MATCH0=0x00000004
UMASK_REMOTE_SF_VICTIM_EXCLUSIVE        0x00
OPTIONS_REMOTE_SF_INCLUSIVE_ONLY        EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_REMOTE_SF_INCLUSIVE_ONLY EVENT_OPTION_MATCH0=0x00000020
UMASK_REMOTE_SF_INCLUSIVE_ONLY          0x00
OPTIONS_REMOTE_SF_DIRBACKED_ONLY        EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_REMOTE_SF_DIRBACKED_ONLY EVENT_OPTION_MATCH0=0x00000040
UMASK_REMOTE_SF_DIRBACKED_ONLY          0x00

#######################################################
#                  M2M == B2CMI                       #
#######################################################

EVENT_M2M_CLOCKTICKS                    0x01 M2M
UMASK_M2M_CLOCKTICKS                    0x00

EVENT_B2CMI_CLOCKTICKS                    0x01 M2M
UMASK_B2CMI_CLOCKTICKS                    0x00

EVENT_IMC_READS                         0x24 M2M
OPTIONS_IMC_READS                       EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_IMC_READS_NORMAL        EVENT_OPTION_MATCH0=0x00000001
UMASK_IMC_READS_NORMAL                  0x01
DEFAULT_OPTIONS_IMC_READS_ALL           EVENT_OPTION_MATCH0=0x00000001
UMASK_IMC_READS_ALL                     0x04
DEFAULT_OPTIONS_IMC_READS_TO_DDR_AS_MEM EVENT_OPTION_MATCH0=0x00000001
UMASK_IMC_READS_TO_DDR_AS_MEM           0x08
DEFAULT_OPTIONS_IMC_READS_TO_DDR_AS_CACHE EVENT_OPTION_MATCH0=0x00000001
UMASK_IMC_READS_TO_DDR_AS_CACHE         0x10

EVENT_IMC_WRITES                        0x25 M2M
OPTIONS_IMC_WRITES                      EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_IMC_WRITES_FULL         EVENT_OPTION_MATCH0=0x00000001
UMASK_IMC_WRITES_FULL                   0x01
DEFAULT_OPTIONS_IMC_WRITES_PARTIAL      EVENT_OPTION_MATCH0=0x00000001
UMASK_IMC_WRITES_PARTIAL                0x02
DEFAULT_OPTIONS_IMC_WRITES_ALL          EVENT_OPTION_MATCH0=0x00000001
UMASK_IMC_WRITES_ALL                    0x10
DEFAULT_OPTIONS_IMC_WRITES_TO_DDR_AS_MEM EVENT_OPTION_MATCH0=0x00000001
UMASK_IMC_WRITES_TO_DDR_AS_MEM          0x20
DEFAULT_OPTIONS_IMC_WRITES_TO_DDR_AS_CACHE EVENT_OPTION_MATCH0=0x00000001
UMASK_IMC_WRITES_TO_DDR_AS_CACHE        0x40
DEFAULT_OPTIONS_IMC_WRITES_NI           EVENT_OPTION_MATCH0=0x00000003
UMASK_IMC_WRITES_NI                     0x00
DEFAULT_OPTIONS_IMC_WRITES_NI_MISS      EVENT_OPTION_MATCH0=0x00000005
UMASK_IMC_WRITES_NI_MISS                0x00

EVENT_TRACKER_INSERT                    0x32 M2M
UMASK_TRACKER_INSERT_CH0                0x04

EVENT_TRACKER_OCCUPANCY                 0x33 M2M
UMASK_TRACKER_OCCUPANCY_CH0             0x01

EVENT_WR_TRACKER_INSERTS                0x40 M2M
UMASK_WR_TRACKER_INSERTS_CH0            0x01

EVENT_TAG_MISS                          0x4B M2M
UMASK_TAG_MISS_RD_CLEAN                 0x01
UMASK_TAG_MISS_RD_DIRTY                 0x02
UMASK_TAG_MISS_WR_CLEAN                 0x04
UMASK_TAG_MISS_WR_DIRTY                 0x08
UMASK_TAG_MISS_CLEAN                    0x05
UMASK_TAG_MISS_DIRTY                    0x0A
UMASK_TAG_MISS_RD_2WAY                  0x10
UMASK_TAG_MISS_WR_2WAY                  0x20

EVENT_PREFCAM_OCCUPANCY                 0x54 M2M
UMASK_PREFCAM_OCCUPANCY_CH0             0x01

EVENT_PREFCAM_INSERTS                   0x56 M2M
UMASK_PREFCAM_INSERTS_CH0_XPT           0x01
UMASK_PREFCAM_INSERTS_XPT_ALLCH         0x01
UMASK_PREFCAM_INSERTS_CH0_UPI           0x02
UMASK_PREFCAM_INSERTS_UPI_ALLCH         0x02

EVENT_DIRECTORY_HIT                     0x1D M2M
UMASK_DIRECTORY_HIT_DIRTY_I             0x01
UMASK_DIRECTORY_HIT_DIRTY_S             0x02
UMASK_DIRECTORY_HIT_DIRTY_A             0x04
UMASK_DIRECTORY_HIT_DIRTY               0x07
UMASK_DIRECTORY_HIT_CLEAN_I             0x08
UMASK_DIRECTORY_HIT_CLEAN_S             0x10
UMASK_DIRECTORY_HIT_CLEAN_A             0x20
UMASK_DIRECTORY_HIT_CLEAN               0x38

EVENT_DIRECTORY_MISS                    0x1E M2M
UMASK_DIRECTORY_MISS_DIRTY_I            0x01
UMASK_DIRECTORY_MISS_DIRTY_S            0x02
UMASK_DIRECTORY_MISS_DIRTY_A            0x04
UMASK_DIRECTORY_MISS_DIRTY              0x07
UMASK_DIRECTORY_MISS_CLEAN_I            0x08
UMASK_DIRECTORY_MISS_CLEAN_S            0x10
UMASK_DIRECTORY_MISS_CLEAN_A            0x20
UMASK_DIRECTORY_MISS_CLEAN              0x38

EVENT_TAG_HIT                           0x1F M2M
UMASK_TAG_HIT_RD_CLEAN                  0x01
UMASK_TAG_HIT_RD_DIRTY                  0x02
UMASK_TAG_HIT_WR_CLEAN                  0x04
UMASK_TAG_HIT_WR_DIRTY                  0x08
UMASK_TAG_HIT_ALL                       0x0F

EVENT_DIRECTORY_UPDATE                  0x21 M2M
OPTIONS_DIRECTORY_UPDATE                EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_DIRECTORY_UPDATE_ANY    EVENT_OPTION_MATCH0=0x00000003
UMASK_DIRECTORY_UPDATE_ANY              0x01
DEFAULT_OPTIONS_DIRECTORY_UPDATE_I2S    EVENT_OPTION_MATCH0=0x00000003
UMASK_DIRECTORY_UPDATE_I2S              0x02
DEFAULT_OPTIONS_DIRECTORY_UPDATE_I2A    EVENT_OPTION_MATCH0=0x00000003
UMASK_DIRECTORY_UPDATE_I2A              0x04
DEFAULT_OPTIONS_DIRECTORY_UPDATE_A2I    EVENT_OPTION_MATCH0=0x00000003
UMASK_DIRECTORY_UPDATE_A2I              0x20
DEFAULT_OPTIONS_DIRECTORY_UPDATE_A2S    EVENT_OPTION_MATCH0=0x00000003
UMASK_DIRECTORY_UPDATE_A2S              0x40
DEFAULT_OPTIONS_DIRECTORY_UPDATE_X2S    EVENT_OPTION_MATCH0=0x00000003
UMASK_DIRECTORY_UPDATE_X2S              0x42
DEFAULT_OPTIONS_DIRECTORY_UPDATE_X2A    EVENT_OPTION_MATCH0=0x00000003
UMASK_DIRECTORY_UPDATE_X2A              0x14
DEFAULT_OPTIONS_DIRECTORY_UPDATE_X2I    EVENT_OPTION_MATCH0=0x00000003
UMASK_DIRECTORY_UPDATE_X2I              0x28
DEFAULT_OPTIONS_DIRECTORY_UPDATE_S2I    EVENT_OPTION_MATCH0=0x00000003
UMASK_DIRECTORY_UPDATE_S2I              0x08
DEFAULT_OPTIONS_DIRECTORY_UPDATE_S2A    EVENT_OPTION_MATCH0=0x00000003
UMASK_DIRECTORY_UPDATE_S2A              0x10
DEFAULT_OPTIONS_DIRECTORY_UPDATE_HIT_ANY EVENT_OPTION_MATCH0=0x00000001
UMASK_DIRECTORY_UPDATE_HIT_ANY          0x01
DEFAULT_OPTIONS_DIRECTORY_UPDATE_HIT_X2S EVENT_OPTION_MATCH0=0x00000001
UMASK_DIRECTORY_UPDATE_HIT_X2S          0x42
DEFAULT_OPTIONS_DIRECTORY_UPDATE_HIT_X2A EVENT_OPTION_MATCH0=0x00000001
UMASK_DIRECTORY_UPDATE_HIT_X2A          0x14
DEFAULT_OPTIONS_DIRECTORY_UPDATE_HIT_X2I EVENT_OPTION_MATCH0=0x00000001
UMASK_DIRECTORY_UPDATE_HIT_X2I          0x28
DEFAULT_OPTIONS_DIRECTORY_UPDATE_MISS_X2S EVENT_OPTION_MATCH0=0x00000002
UMASK_DIRECTORY_UPDATE_MISS_X2S         0x42
DEFAULT_OPTIONS_DIRECTORY_UPDATE_MISS_X2A EVENT_OPTION_MATCH0=0x00000002
UMASK_DIRECTORY_UPDATE_MISS_X2A         0x14
DEFAULT_OPTIONS_DIRECTORY_UPDATE_MISS_X2I EVENT_OPTION_MATCH0=0x00000002
UMASK_DIRECTORY_UPDATE_MISS_X2I         0x28

EVENT_DIRECTORY_LOOKUP                  0x20 M2M
UMASK_DIRECTORY_LOOKUP_ANY              0x01
UMASK_DIRECTORY_LOOKUP_STATE_I          0x02
UMASK_DIRECTORY_LOOKUP_STATE_S          0x04
UMASK_DIRECTORY_LOOKUP_STATE_A          0x08

EVENT_DIRECT2UPI_NOT_TAKEN_DIRSTATE_EGRESS  0x1A M2M
UMASK_DIRECT2UPI_NOT_TAKEN_DIRSTATE_EGRESS  0x01

EVENT_DIRECT2UPI_NOT_TAKEN_CREDITS_EGRESS   0x1B M2M
UMASK_DIRECT2UPI_NOT_TAKEN_CREDITS_EGRESS   0x01

EVENT_DIRECT2CORE_TAKEN                 0x16 M2M
UMASK_DIRECT2CORE_TAKEN                 0x01

EVENT_DIRECT2CORE_NOT_TAKEN_DIRSTATE    0x17 M2M
UMASK_DIRECT2CORE_NOT_TAKEN_DIRSTATE    0x01

EVENT_DIRECT2CORE_TXN_OVERRIDE          0x18 M2M
UMASK_DIRECT2CORE_TXN_OVERRIDE          0x01

EVENT_DIRECT2UPI_TAKEN                  0x19 M2M
UMASK_DIRECT2UPI_TAKEN                  0x01

EVENT_DIRECT2UPI_NOT_TAKEN_DIRSTATE     0x1A M2M
UMASK_DIRECT2UPI_NOT_TAKEN_DIRSTATE     0x01

EVENT_DIRECT2UPI_NOT_TAKEN_CREDITS      0x1B M2M
UMASK_DIRECT2UPI_NOT_TAKEN_CREDITS      0x01

EVENT_DIRECT2UPI_TXN_OVERRIDE           0x1C M2M
UMASK_DIRECT2UPI_TXN_OVERRIDE           0x01

#######################################################
#              IIO == IIO                             #
#######################################################
EVENT_IIO_CLOCKTICKS                    0x01 IBOX
UMASK_IIO_CLOCKTICKS                    0x00

EVENT_IBOX_CLOCKTICKS                    0x01 IBOX
UMASK_IBOX_CLOCKTICKS                    0x00

EVENT_IIO_DATA_REQ_OF_CPU                   0x83 IBOX0C0|IBOX0C1|IBOX1C0|IBOX1C1|IBOX2C0|IBOX2C1|IBOX3C0|IBOX3C1|IBOX4C0|IBOX4C1|IBOX5C0|IBOX5C1|IBOX6C0|IBOX6C1|IBOX7C0|IBOX7C1|IBOX8C0|IBOX8C1|IBOX9C0|IBOX9C1|IBOX10C0|IBOX10C1|IBOX11C0|IBOX11C1|IBOX12C0|IBOX12C1|IBOX13C0|IBOX13C1|IBOX14C0|IBOX14C1|IBOX15C0|IBOX15C1
OPTIONS_IIO_DATA_REQ_OF_CPU                 EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART1 EVENT_OPTION_MATCH0=0x00070020
UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART1   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART2 EVENT_OPTION_MATCH0=0x00070040
UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART2   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART3 EVENT_OPTION_MATCH0=0x00070080
UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART3   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART4 EVENT_OPTION_MATCH0=0x00070100
UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART4   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART5 EVENT_OPTION_MATCH0=0x00070200
UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART5   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART6 EVENT_OPTION_MATCH0=0x00070400
UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART6   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART7 EVENT_OPTION_MATCH0=0x00070800
UMASK_IIO_DATA_REQ_OF_CPU_MEM_WRITE_PART7   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART1 EVENT_OPTION_MATCH0=0x00070020
UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART1    0x04
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART2 EVENT_OPTION_MATCH0=0x00070040
UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART2    0x04
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART3 EVENT_OPTION_MATCH0=0x00070080
UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART3    0x04
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART4 EVENT_OPTION_MATCH0=0x00070100
UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART4    0x04
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART5 EVENT_OPTION_MATCH0=0x00070200
UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART5    0x04
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART6 EVENT_OPTION_MATCH0=0x00070400
UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART6    0x04
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_MEM_READ_PART7 EVENT_OPTION_MATCH0=0x00070800
UMASK_IIO_DATA_REQ_OF_CPU_MEM_READ_PART7    0x04

EVENT_TXN_DATA_REQ_OF_CPU                   0x84 IBOX0C0|IBOX0C1|IBOX1C0|IBOX1C1|IBOX2C0|IBOX2C1|IBOX3C0|IBOX3C1|IBOX4C0|IBOX4C1|IBOX5C0|IBOX5C1|IBOX6C0|IBOX6C1|IBOX7C0|IBOX7C1|IBOX8C0|IBOX8C1|IBOX9C0|IBOX9C1|IBOX10C0|IBOX10C1|IBOX11C0|IBOX11C1|IBOX12C0|IBOX12C1|IBOX13C0|IBOX13C1|IBOX14C0|IBOX14C1|IBOX15C0|IBOX15C1
OPTIONS_TXN_DATA_REQ_OF_CPU                 EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART1 EVENT_OPTION_MATCH0=0x00070020
UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART1   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART2 EVENT_OPTION_MATCH0=0x00070040
UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART2   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART3 EVENT_OPTION_MATCH0=0x00070080
UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART3   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART4 EVENT_OPTION_MATCH0=0x00070100
UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART4   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART5 EVENT_OPTION_MATCH0=0x00070200
UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART5   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART6 EVENT_OPTION_MATCH0=0x00070400
UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART6   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART7 EVENT_OPTION_MATCH0=0x00070800
UMASK_TXN_DATA_REQ_OF_CPU_MEM_WRITE_PART7   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART1 EVENT_OPTION_MATCH0=0x00070020
UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART1    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART2 EVENT_OPTION_MATCH0=0x00070040
UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART2    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART3 EVENT_OPTION_MATCH0=0x00070080
UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART3    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART4 EVENT_OPTION_MATCH0=0x00070100
UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART4    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART5 EVENT_OPTION_MATCH0=0x00070200
UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART5    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART6 EVENT_OPTION_MATCH0=0x00070400
UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART6    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_OF_CPU_MEM_READ_PART7 EVENT_OPTION_MATCH0=0x00070800
UMASK_TXN_DATA_REQ_OF_CPU_MEM_READ_PART7    0x04


EVENT_IIO_DATA_REQ_BY_CPU                   0xC0 IBOX0C2|IBOX0C3|IBOX1C2|IBOX1C3|IBOX2C2|IBOX2C3|IBOX3C2|IBOX3C3|IBOX4C2|IBOX4C3|IBOX5C2|IBOX5C3|IBOX6C2|IBOX6C3|IBOX7C2|IBOX7C3|IBOX8C2|IBOX8C3|IBOX9C2|IBOX9C3|IBOX10C2|IBOX10C3|IBOX11C2|IBOX11C3|IBOX12C2|IBOX12C3|IBOX13C2|IBOX13C3|IBOX14C2|IBOX14C3|IBOX15C2|IBOX15C3
OPTIONS_IIO_DATA_REQ_BY_CPU                 EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART1 EVENT_OPTION_MATCH0=0x00070020
UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART1   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART2 EVENT_OPTION_MATCH0=0x00070040
UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART2   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART3 EVENT_OPTION_MATCH0=0x00070080
UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART3   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART4 EVENT_OPTION_MATCH0=0x00070100
UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART4   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART5 EVENT_OPTION_MATCH0=0x00070200
UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART5   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART6 EVENT_OPTION_MATCH0=0x00070400
UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART6   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART7 EVENT_OPTION_MATCH0=0x00070800
UMASK_IIO_DATA_REQ_BY_CPU_MEM_WRITE_PART7   0x01
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_WRITE_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0
UMASK_IIO_DATA_REQ_BY_CPU_PEER_WRITE_ALL_PARTS 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_READ_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0
UMASK_IIO_DATA_REQ_BY_CPU_PEER_READ_ALL_PARTS 0x08

#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART1 EVENT_OPTION_MATCH0=0x00070020
#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART1    0x04
#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART2 EVENT_OPTION_MATCH0=0x00070040
#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART2    0x04
#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART3 EVENT_OPTION_MATCH0=0x00070080
#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART3    0x04
#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART4 EVENT_OPTION_MATCH0=0x00070100
#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART4    0x04
#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART5 EVENT_OPTION_MATCH0=0x00070200
#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART5    0x04
#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART6 EVENT_OPTION_MATCH0=0x00070400
#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART6    0x04
#DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_MEM_READ_PART7 EVENT_OPTION_MATCH0=0x00070800
#UMASK_IIO_DATA_REQ_BY_CPU_MEM_READ_PART7    0x04


EVENT_TXN_DATA_REQ_BY_CPU                   0xC1 IBOX0C2|IBOX0C3|IBOX1C2|IBOX1C3|IBOX2C2|IBOX2C3|IBOX3C2|IBOX3C3|IBOX4C2|IBOX4C3|IBOX5C2|IBOX5C3|IBOX6C2|IBOX6C3|IBOX7C2|IBOX7C3|IBOX8C2|IBOX8C3|IBOX9C2|IBOX9C3|IBOX10C2|IBOX10C3|IBOX11C2|IBOX11C3|IBOX12C2|IBOX12C3|IBOX13C2|IBOX13C3|IBOX14C2|IBOX14C3|IBOX15C2|IBOX15C3
OPTIONS_TXN_DATA_REQ_BY_CPU                 EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART1 EVENT_OPTION_MATCH0=0x00070020
UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART1   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART2 EVENT_OPTION_MATCH0=0x00070040
UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART2   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART3 EVENT_OPTION_MATCH0=0x00070080
UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART3   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART4 EVENT_OPTION_MATCH0=0x00070100
UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART4   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART5 EVENT_OPTION_MATCH0=0x00070200
UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART5   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART6 EVENT_OPTION_MATCH0=0x00070400
UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART6   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART7 EVENT_OPTION_MATCH0=0x00070800
UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_PART7   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_WRITE_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0
UMASK_TXN_DATA_REQ_BY_CPU_MEM_WRITE_ALL_PARTS   0x01
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_PEER_WRITE_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0
UMASK_TXN_DATA_REQ_BY_CPU_PEER_WRITE_ALL_PARTS   0x02
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART1 EVENT_OPTION_MATCH0=0x00070020
UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART1    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART2 EVENT_OPTION_MATCH0=0x00070040
UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART2    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART3 EVENT_OPTION_MATCH0=0x00070080
UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART3    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART4 EVENT_OPTION_MATCH0=0x00070100
UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART4    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART5 EVENT_OPTION_MATCH0=0x00070200
UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART5    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART6 EVENT_OPTION_MATCH0=0x00070400
UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART6    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_PART7 EVENT_OPTION_MATCH0=0x00070800
UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_PART7    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_MEM_READ_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0
UMASK_TXN_DATA_REQ_BY_CPU_MEM_READ_ALL_PARTS    0x04
DEFAULT_OPTIONS_TXN_DATA_REQ_BY_CPU_PEER_READ_ALL_PARTS EVENT_OPTION_MATCH0=0x00070FF0
UMASK_TXN_DATA_REQ_BY_CPU_PEER_READ_ALL_PARTS    0x08

#######################################################
#              IRP == IRP                             #
#######################################################
EVENT_IRP_CLOCKTICKS                                0x01 IRP
UMASK_IRP_CLOCKTICKS                                0x00

EVENT_TRANSACTIONS                                  0x11 IRP
UMASK_TRANSACTIONS_WR_PRE                           0x08

EVENT_FAF_INSERT                                    0x18 IRP
UMASK_FAF_INSERT                                    0x00

EVENT_CACHE_TOTAL_OCCUPANCY                         0x0F IRP
UMASK_CACHE_TOTAL_OCCUPANCY_MEM                     0x04

EVENT_FAF_OCCUPANCY                                 0x19 IRP
UMASK_FAF_OCCUPANCY                                 0x00

EVENT_MISC1                                         0x1F IRP
UMASK_MISC1_LOST_FWD                                0x10

#######################################################
#                 PBOX == B2CXL                       #
#######################################################

EVENT_PBOX_CLOCKTICKS                               0x01 PBOX
UMASK_PBOX_CLOCKTICKS                               0x00

EVENT_B2CXL_CLOCKTICKS                               0x01 PBOX
UMASK_B2CXL_CLOCKTICKS                               0x00

#######################################################
#                 RBOX == B2UPI                       #
#######################################################

EVENT_RBOX_CLOCKTICKS                               0x01 RBOX
UMASK_RBOX_CLOCKTICKS                               0x00

EVENT_B2UPI_CLOCKTICKS                               0x01 RBOX
UMASK_B2UPI_CLOCKTICKS                               0x00

#######################################################
#                  PCU == PCU                       #
#######################################################

EVENT_PCU_CLOCKTICKS                                0x01 PCU
UMASK_PCU_CLOCKTICKS                                0x00

EVENT_POWER_STATE_OCCUPANCY_CORES_C0                0x35 PCU
UMASK_POWER_STATE_OCCUPANCY_CORES_C0                0x00

EVENT_POWER_STATE_OCCUPANCY_CORES_C6                0x37 PCU
UMASK_POWER_STATE_OCCUPANCY_CORES_C6                0x00

EVENT_FREQ_MAX_LIMIT_THERMAL_CYCLES                 0x04 PCU
UMASK_FREQ_MAX_LIMIT_THERMAL_CYCLES                 0x00

EVENT_FREQ_MAX_POWER_CYCLES                         0x05 PCU
UMASK_FREQ_MAX_POWER_CYCLES                         0x00

EVENT_FREQ_TRANS_CYCLES                             0x74 PCU
UMASK_FREQ_TRANS_CYCLES                             0x00

EVENT_PKG_RESIDENCY_C2E_CYCLES                      0x2B PCU
UMASK_PKG_RESIDENCY_C2E_CYCLES                      0x00

EVENT_PKG_RESIDENCY_C6_CYCLES                       0x2D PCU
UMASK_PKG_RESIDENCY_C6_CYCLES                       0x00

EVENT_POWER_STATE_OCCUPANCY_CORES_C3                0x36 PCU
UMASK_POWER_STATE_OCCUPANCY_CORES_C3                0x00

EVENT_PROCHOT_EXTERNAL_CYCLES                       0x0A PCU
UMASK_PROCHOT_EXTERNAL_CYCLES                       0x00

EVENT_PROCHOT_INTERNAL_CYCLES                       0x09 PCU
UMASK_PROCHOT_INTERNAL_CYCLES                       0x00
